Method of making non-volatile semiconductor memory arrays
AssigneeHoltek Microelectronics, Inc.
InventorsChen Ling, Siu-han Liao
Life of this patent
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Abstract
A new structure of a non-volatile semiconductor memory cell array and a method of fabricating the memory arrays. The circuit layout of the memory array not only comprises of the conventional floating gates, control gates, cell sources and cell drains, but also adds the local source regions to increase the coupling ratio. Besides, the new design can reduce the number of metal contact windows, further increase the packing density of the memory array. Furthermore, an additional isolation region is formed between two bit lines so as to increase the distance between two bit lines, which can minimize the possibility of cross talk due to shirking spacing.
Claims7
A method for fabricating a non-volatile semiconductor memory cell, comprising the steps of:
- (a) providing a P-type semiconductor substrate;
- (b) forming a field oxide region and a tunnel oxide layer on said substrate;
- (c) forming a first polysilicon layer on said substrate;
- (d) sequentially depositing a first dielectric layer, a metal polycide layer, and a second dielectric layer overlaying said polysilicon layer to form a multi-layered structure;
- (e) forming a plurality of stacked gates from said multi-layered structure using lithography and plasma-etching techniques, wherein each stacked gate containing, from top to bottom, said second dielectric layer, said metal polycide layer, said first dielectric layer, and said first polysilicon layer, and said first polysilicon layer becoming a floating gate and said metal polycide layer becoming a control gate;
- (f) using said stacked gates as a mask, ion-implanting N-type impurities into a predetermined region of said substrate to form cell sources and cell drains;
- (g) growing a cell source/drain oxide layer overlaying entire said substrate;
- (h) depositing a thick oxide layer overlaying entire said substrate including said source drain region and covering entire said stacked gates
- (i) forming a photoresist to protect the portion of said thick oxide layer which overlays said cell sources as well as cover sidewalls of said stacked gates adjacent to said cell sources;
- (j) using an anisotropic etching technique to expose said cell drains and form sidewall spacers from said thick oxide layer adjacent to said cell drains, while leaving said cell sources and the portion of said stacked gates connected to said cell sources protected by a remaining portion of said thick oxide layer;
- (k) depositing a conducting layer overlaying entire said substrate, then using lithography and plasma-etching techniques to form local sources and local bitlines from said cell drains in alternating locations, wherein said cell sources are insulated from said local sources and said local bitlines by said thick oxide layer, and said local sources and said local bitlines are formed without the need to specifically form contacts thereto.
Dependencies are inferred from the claim text.