US 5,966,600 A · DRAM process with a multilayer stack structure

Abstract

A DRAM is formed using a process which uses few critical lithography steps and which provides capacitor electrodes and bit line contacts in a self-aligned manner in a common set of processing steps. A multilayer stack including a gate oxide layer, a gate electrode layer, an etch stop layer, and a thicker sacrificial layer are provided over the active device regions of a semiconductor substrate. Photolithography and etching define gate electrodes and wiring lines with patterned etch stop layers and patterned sacrificial layers over and self-aligned with the gate electrodes and wiring lines. Source/drain regions are formed self aligned to the patterned stacks and then an insulating spacer is provided alongside the edges of the gate electrodes. A relatively thin, conformal polysilicon layer is provided over the patterned stacks and in contact with the source/drain regions adjacent the gate electrodes. A planarizing layer is provided to fill in the gaps over the polysilicon layer between the stacks of gate electrodes, patterned etch stop layers and patterned sacrificial layers. A polishing process is performed to remove the conductive layer over the patterned sacrificial layers. The exposed sacrificial layer and the planarizing layers are removed to provide lower capacitor electrodes with vertically extending fins and bit line contacts with landing pads that facilitate making contacts to the bit line contacts. Processing continues to provide a capacitor dielectric layer, an upper capacitor electrode and a bit line contact to complete the DRAM.

Claims23

Dependent claims

A method of making an integrated circuit device comprising the steps of:

providing a gate electrode layer and a sacrificial layer in sequence over a substrate to form a multilayer stack structure over the substrate;
patterning the multilayer stack structure to provide a pattern of gate electrodes covered by a like pattern of sacrificial structures formed from the sacrificial layer and aligned with the pattern of gate electrodes;
forming source/drain regions along sides of the gate electrodes;
providing a conductive layer over the pattern of sacrificial structures, the conductive layer extending over one of the sacrificial structures and a corresponding one of the gate electrodes to make contact with first and second source/drain regions on either side of the one gate electrode, a horizontal portion of the conductive layer extending across an upper surface of the one sacrificial structure;
removing at least part of the horizontal portion of the conductive layer to define a first conductive structure in contact with the first source/drain region and a second conductive structure in contact with the second source/drain region;
removing at least part of the one sacrificial structure to expose a vertically extending surface of the first conductive structure previously covered by the removed part of the one sacrificial structure;
forming a dielectric layer over exposed surfaces of the first conductive structure;
forming a conductive upper electrode over the dielectric layer;
providing an interlayer insulating layer over the conductive upper electrode, and
forming a bit line contact to the second conductive structure.

7 more elements

A method of making an integrated circuit device comprising the steps of:

providing a gate oxide layer, a gate electrode layer, an etch stop layer and a sacrificial layer over an active device region of a substrate to form a multilayer stack structure;
forming an etching mask on the multilayer stack structure and then etching first through the sacrificial layer, through the etch stop layer and then through the gate electrode layer using the etching mask to provide a pattern of gate electrodes covered by a like pattern of sacrificial structures;
forming source/drain regions along sides of the gate electrodes by ion implantation aligned with the pattern of sacrificial structures;
depositing an insulating spacer layer over the pattern of sacrificial structures and etching back the insulating spacer layer to provide insulating spacer structures adjacent the edges of the gate electrodes;
providing a polysilicon layer over the pattern of sacrificial structures, the polysilicon layer extending over sides of one of the sacrificial structures and adjacent the sides of a corresponding one of the gate electrodes to make contact with first and second source/drain regions on either side of the one gate electrode, a horizontal portion of the polysilicon layer extending across an upper surface of the sacrificial structure;
depositing a planarizing layer over the polysilicon layer;
removing part of the polysilicon layer to expose a surface of the sacrificial structure, leaving a first polysilicon structure in contact with the first source/drain region and a second polysilicon structure in contact with the second source/drain region;
etching the sacrificial structure to expose a first vertically extending surface of the first conductive structure previously covered by the sacrificial structure;
etching the planarizing layer to expose a second vertically extending surface of the first conductive structure previously covered by the planarizing layer;
forming a dielectric layer over the first and second vertically extending surfaces of the first conductive structure;
forming a conductive upper electrode over the dielectric layer;
providing an interlayer insulating layer over the conductive upper electrode;
and
forming a bit line contact to the second conductive structure.

11 more elements

Dependencies are inferred from the claim text.

DRAM process with a multilayer stack structure

Life of this patent

DRAM process with a multilayer stack structure

Life of this patent

Abstract

Claims23