Capacitor designing method of MOS transistor

A method for designing capacitor of a MOS transistor, in which a drain region and a source region at both side of a gate channel region on a diffusion layer are shorted, and a capacitor having a capacitance C, a channel length L and a channel width W is formed by a portion where a gate electrode and said gate channel region overlap, with taking a capacitance of the overlapping portion of said gate electrode and said gate channel region per unit area being K1 and a resistivity of said gate channel region being K2, for application to a circuit, in which charge and discharge of said capacitor is performed at high speed, comprising a step of:

• setting said channel length L and said channel width W of said MOS transistor in such a manner that a period t1 for propagating a potential from a center portion of said gate channel to said drain region or said source region, and a period t2 from rising of potential of said gate electrode from a grounding potential to a power source potential to elevating of a potential in said diffusion layer region opposing to said gate electrode from the grounding potential to the power source potential are substantially equal to each other.