Semiconductor memory device with improved read speed

A semiconductor memory device including a memory matrix comprising a plurality of memory cells, each of said plurality of memory cells comprising:

• a semiconductor substrate;
• first memory diffusion layers formed on said semiconductor substrate so as to operate as source regions of memory cells;
• second memory diffusion layers formed on said semiconductor substrate so as to operate as drain regions of the memory cells, each of said second memory diffusion layers being parallel with each of said first memory diffusion layers;
• a first insulating film formed on said semiconductor substrate;
• floating gates formed of a first conductive material and formed on said first insulating film so as to form respective memory cells, such that each of said floating gates is contiguous with one of said first memory diffusion layer and said second memory diffusion layer, and is laterally offset by a predetermined distance from another one of said first memory diffusion layer and said second memory diffusion layer, said floating gates for respective memory cells being physically separate from each other;
• a second insulating film formed on said semiconductor substrate;
• and
• gate electrode structures each formed on a corresponding one of said floating gates, each of said gate electrode structures including a selection gate of the memory cell, said selection gate being formed of a second conductive material and formed on said second insulating film so as to cover the floating gate and to extend in a direction perpendicular to a direction in which said first memory diffusion layer and said second memory diffusion layer extend,
• the semiconductor substrate surface underneath each of said floating gates operating as a memory channel of the memory cell, and the semiconductor substrate between the floating gate and said another one of said first memory diffusion layer and said second memory diffusion layer operating as a selection channel of the memory cell, wherein
• said memory matrix is segmented into a plurality of blocks each including a plurality of memory cells such that one of said first memory diffusion layer and said second memory diffusion layer connected to a sense amplifier in a read operation is divided into independent segments corresponding to said plurality of blocks, and such that said independent segments are connected to a common metal bit line via block selection transistors provided for respective blocks, and
• each of said block selection transistors is a MOS transistor comprising:
• a source region and a drain region formed of the same material as said first memory diffusion layer and said second memory diffusion layer;
• and
• a gate electrode formed of the second conductive material.