Semiconductor device with MOS capacitor and fabrication method thereof

Abstract

A semiconductor device is provided, which is able to suppress the capacitance lowering of the capacitor due to a voltage applied across the capacitor. The device includes a well formed in a semiconductor substrate of a first conductivity type. The well is of a second conductivity type opposite to the first conductivity type. A surface area of the well is divided into at least first and second parts. The first part is of the first conductivity type and the second part is of the second conductivity type. An insulating layer is formed on the well to be contacted with the first and second parts. An electrode is formed on the insulating layer and is located over the first and second parts. The capacitor formed by the well, the insulating layer, and the electrode is equivalent to a capacitor composed by a first subcapacitor including the first part and a second subcapacitor including the second part. The dopant concentration of the first and second parts of the well may be higher or lower than that of the remaining well.

Dependencies are inferred from the claim text.