Semiconductor device and a method of fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorJi-Hyoung Yoo
Life of this patent
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Abstract
A CMOS device is disclosed in which p-channel and n-channel MOS transistors are formed on the same substrate. Each of the MOS transistors has a gate insulating layer formed on the substrate; a gate having a gate body and a spacer formed on both sidewalls of the gate body; a drain region of a first conductivity type formed in the substrate and beneath the gate body; a channel region of a second conductivity type formed at both sides of the first heavily doped impurity region and beneath the spacer; and a source region of the first conductivity type formed in the substrate and between the channel region and the device isolating region. With this CMOS device, the channel length can be controlled to about 0.1 mm and less and hot-carrier effect can be minimized.
Claims17
A semiconductor device, comprising:
- n-channel and p-channel MOS (metal oxide semiconductor) transistors which are electrically isolated by a device isolating region on a same SOI (silicon on insulator) substrate;
- and
- each of the MOS transistors having
- a gate insulating layer formed on the substrate;
- a gate having a gate body and a spacer formed on both sidewalls of the gate body;
- a drain region of a first conductivity type formed in the substrate and beneath the gate body;
- a channel region of a second conductivity type formed at both sides of the drain region and beneath the spacer;
- and
- a source region of the first conductivity type formed in the substrate and between the channel regions and the device isolating region.
A semiconductor device comprising:
- a silicon substrate;
- two well regions of different conductivity type formed on the same silicon substrate;
- n-channel and p-channel MOS (metal oxide semiconductor) transistors which are respectively formed on the two well regions and electrically isolated by a device isolating region on the same silicon substrate;
- and
- each of the MOS transistors having a gate insulating layer formed on the substrate;
- a gate having a gate body and a spacer formed on both sidewalls of the gate body;
- a drain region of a first conductivity type formed in the substrate and beneath the gate body;
- a channel region of a second conductivity type formed at both sides of the drain region and beneath the spacer;
- and a source region of the first conductivity type formed in the substrate and between the channel region and the device isolating region.
A semiconductor device comprising:
- n-channel and p-channel MOS (metal oxide semiconductor) transistors which are electrically isolated by a device isolating region on a same SOI (silicon on insulator) substrate;
- and
- each of the MOS transistors having a gate insulating layer formed on the substrate;
- an insulator formed on a part of the gate insulating layer;
- a gate surrounding the insulator and having a gate body and a spacer formed on both sidewalls of the gate body;
- a heavily doped drain region of a first conductivity type formed in the substrate and beneath the insulator;
- a lightly doped drain region of the first conductivity type formed at both sides of the heavily doped drain region and beneath the gate body;
- a channel region of a second conductivity type formed between the lightly doped drain region and the device isolating region and beneath the spacer;
- and a source region of the first conductivity type formed in the substrate and between the channel region and the device isolating region.
A semiconductor device comprising:
- a silicon substrate;
- two well regions of different conductivity type formed on the same silicon substrate;
- n-channel and p-channel MOS (metal oxide semiconductor) transistors which are respectively formed on the two well regions and electrically isolated by a device isolating region on the same silicon substrate;
- and
- each of the MOS transistors having a gate insulating layer formed on the substrate;
- an insulator formed on a part of the gate insulating layer;
- a gate surrounding the insulator and having a gate body and a spacer formed on both sidewalls of the gate body;
- a heavily doped drain region of a first conductivity type formed in the substrate and beneath the insulator;
- a lightly doped drain region of the first conductivity type formed at both sides of the heavily doped drain region and beneath the gate body;
- a channel region of a second conductivity type formed between the lightly doped drain region and the device isolating region and beneath the spacer;
- and a source region of the first conductivity type formed in the substrate and between the channel region and the device isolating region.
Dependencies are inferred from the claim text.