Metal/amorphous material/metal antifuse structure with a barrier enhancement layer

Abstract

An amorphous-silicone-based antifuse structure has been invented for VLSI (Very Large Scale Integration circuits) FPGA's (Fields Programmable Gate Array) applications. The structure comprises from top to bottom a first Al layer/a first i-a-SiC:H layer/an i-a-SiH layer/a second i-a-SiC:H layer/a second Al layer, which is basically a MIM (Metal/Insulator/Metal) structure. The MIM structure offers such major advantages as simple for preparation and low in cost. Due to use of the Al layer as an electrode metal and use of a PECVD system for the preparation of the amorphous silicon materials, the antifuse structure is compatible with that of general VLSI devices. In addition, due to a difference in the thickness of barrier enhancement layers in the first and the second i-a-SiC:H layer, a programmed voltage can be adjusted easily and applied in many fields. This structure has a very low on-resistance as the antifuse structure breakdown. The anitifuse has a high resistance (i.e. OFF state) under an unprogrammable state and its leakage current under 5V bias is smaller than 100 nA.

Dependencies are inferred from the claim text.