Gate pattern formation using a bottom anti-reflective coating

#The present invention relates to semiconductor devices and manufacturing processes, and more particularly to methods for forming conductive gates within a semiconductor device using a bottom anti-reflective coating (BARC).

#A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration (ULSI) has resulted in continued shrinking of device and circuit dimensions and features. In integrated circuits having field-effect transistors, for example, one very important process step is the formation of the gate for each of the transistors, and in particular the dimensions of the gate. In many applications, the performance characteristics (e.g., switching speed) and size of the transistor are functions of the size (e.g., width) of the transistor's gate. Thus, for example, a narrower gate tends to produce a higher performance transistor (e.g., faster) that is inherently smaller in size (e.g., narrower width).

#As is often the case, however, there are limitations to existing techniques that reduce their effectiveness or even exclude their use in fabricating the next generation of integrated circuit devices. For example, the limitations of conventional lithographic techniques and tools, which are used to pattern the gates during fabrication, are quickly being realized. According, there is a continuing need for more efficient and effective fabrication processes for forming transistor gates that are smaller and/or exhibit higher performance.

#The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements in which;

#FIG. 1 depicts a cross-section of a portion of a semiconductor wafer which has been prepared for gate conductor formation, in accordance one embodiment of the present invention;

#FIG. 2 depicts a cross-section of the portion of FIG. 1 following a selective BARC etching process, in accordance one embodiment of the present invention;

#The process steps and structures described below do not form a complete process flow for manufacturing integrated circuits. The present invention can be practiced in conjunction with integrated circuit fabrication techniques currently used in the art, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the present invention. The figures representing cross-sections of portions of an integrated circuit device during fabrication are not drown to scale, but instead are drawn so as to illustrate the important features of the present invention.

#In accordance with an embodiment of the present invention, there is provided a process for forming at least one gate conductor within an integrated circuit using a silicone oxynitride (e.g., SiO.sub.x N.sub.y, referred to hereinafter as SiON) film as a bottom anti-reflective coating (BARC). The process, in accordance with the present invention, eliminates the need to use an organic spin-on BARC, allows for better critical dimension (CD) uniformity across varying circuit densities, and increases the depth of focus during subsequent patterning steps. As such, the present invention provides better process control over the gate formation and eliminates the potential for defects traceable to the use of an organic spin-on BARC.

#FIG. 1 depicts a cross-section of a portion 10 of a semiconductor device being fabricated on a semiconductor wafer, in accordance with the present invention. Portion 10 includes a wafer stack 11 having a substrate 12, a gate dielectric 14, a gate conductive layer 16, and a BARC 18. As depicted, there is also a resist mask 20 that has been patterned on top of BARC 18. In accordance with one embodiment of the present invention, substrate 12 includes a heavily-doped silicon layer, approximately 2 mm thick, and a lightly-doped epitaxial (epi) layer, approximately 4 .mu.m thick, which is grown on the heavily-doped silicon layer. Gate dielectric layer 14 acts as a barrier between gate conductive layer 16 and substrate 12. In one embodiment of the present invention, gate dielectric layer 14 is an oxide layer, approximately 55 .ANG. thick, which is formed on top of substrate 12. Gate conductive layer 16, in one embodiment, is a layer of polycrystalline silicon, approximately 1,700 .ANG. thick, which is formed on top of gate dielectric layer 14.