Reduction of polysilicon contact resistance by nitrogen implantation
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJenn-Ming Huang
Life of this patent
Estimating the term…
Abstract
Making low resistance contact between two silicon layers has been accomplished by implanting nitrogen ions into a freshly formed silicon surface thereby forming a nitrogen rich layer at the surface which suppresses formation of a surface layer of oxide, the normal 20-30 Angstrom thick native oxide being now restricted to 3 or 4 Angstroms. When a layer of polysilicon is deposited onto this nitrided surface good, low resistance electrical contact is made. The process is fully compatible with existing methods for the manufacture of integrated circuits. An example of its application to making low resistance contact to a FET gate electrode is given.
Claims16
A method for reducing polysilicon contact resistance, comprising the steps of:
- providing a body of single crystal silicon having a surface;
- removing an amount of said surface, thereby exposing a fresh surface;
- before said fresh surface is exposed to air, implanting nitrogen ions, at a voltage and at a dosage, in said fresh surface to a depth;
- and
- depositing a layer of polysilicon on said implanted surface whereby contact resistance between the layer of polysilicon and said implanted surface is reduced.
A method for reducing polysilicon contact resistance, comprising the steps of:
- providing a first layer of polysilicon, having a surface, on a substrate;
- removing an amount of said surface, thereby exposing a fresh surface;
- before said fresh surface is exposed to air, implanting nitrogen ions, at a voltage and at a dosage, in said fresh surface to a depth;
- and
- depositing a second layer of polysilicon on said implanted surface whereby contact resistance between the layer of polysilicon and said implanted surface is reduced.
A process for forming a self-aligned polysilicon contact in an integrated circuit, comprising the steps of:
- providing a silicon body;
- forming a layer of gate oxide on said silicon body;
- depositing a first layer of polysilicon on the layer of gate oxide;
- patterning and etching said first layer of polysilicon and layer of gate oxide to form a gate electrode;
- forming self-aligned source and drain regions adjacent to the gate electrode;
- depositing a dielectric layer over the gate and the source and drain regions;
- patterning and etching the dielectric layer to form a gate contact window, having a width, thereby exposing a fresh gate surface;
- before said fresh gate surface is exposed to air, implanting nitrogen ions, at a voltage and at a dosage, in said fresh gate surface to a depth;
- and
- depositing a second layer of polysilicon on said dielectric layer and on said implanted gate surface whereby contact resistance between the layer of polysilicon and said implanted surface is reduced.
Dependencies are inferred from the claim text.