CMOS process for forming planarized twin wells
AssigneeTexas Instruments - Acer Incorporated
InventorShye-Lin Wu
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AssigneeTexas Instruments - Acer Incorporated
InventorShye-Lin Wu
Estimating the term…
This invention proposes a process to form planarized twin-wells for CMOS devices. After depositing a pad oxide and a silicon nitride layers, a high-energy phosphorus ion implantation is performed to form the N-well by using a photoresist as s mask. A thick oxide layer deposited by liquid phase deposition process is then grown on the N-well region part of the silicon nitride layer, but not on the photoresist. After stripping the photoresist, a high-energy boron ion implantation is carried out to form the P-well by using the LPD-oxide layer as a mask. The thick LPD-oxide layer is removed by BOE or HF solution. A high temperature steam oxidation is performed to grow field oxides. The dopants are activated and driven in to form twin-wells at this step. After removing the pad oxide and the silicon nitride layer, the CMOS device is fabricated by standard processes.
A process for forming planarized twin wells, said process comprising:
Dependencies are inferred from the claim text.