US 5,963,799 AGranted

Blanket well counter doping process for high speed/low power MOSFETs

AssigneeTexas Instruments - Acer Incorporated

InventorShye-Lin Wu

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Abstract

The present invention is a blanket well counter doping process for high speed and low power MOSFETs. An N-well region and a P-well region are in a substrate and a pad silicon oxide layer is on the substrate. A silicon nitride pattern is formed on the pad oxide layer to define active regions of the N-well and P-well region, a field oxide region is formed by using the silicon nitride as a mask. Afterward, an N-type ion implantation is implemented for anti-punchthrough region of the N-well region. A blanket P-type ion implantation is performed for N-well counter doping and P-well doping. A P-type low-energy and low-dosage ions is then implanted into the substrate for the threshold voltage adjustment. The last implantation stage is N-type and low dose to form a P-well counter doping region and an N-well doping region. Finally, a gate structure is manufactured on the N-well region and the P-well region and source/drain regions are fabricated in the P-well region and the N-well region to form an NMOS device and a PMOS device.

Claims17

Dependent claims

A method to manufacture a complementary metal oxide semiconductor device, the method comprising the steps of:

providing a substrate having a P-well region and an N-well region;
forming a pad oxide layer on said substrate;
forming a silicon nitride pattern on said pad oxide layer to define active regions of said P-well region and an N-well region;
forming a field oxide region on said substrate;
removing said silicon nitride pattern;
performing a first ion implantation with N-type conducting dopants on said N-well region to form an anti-punchthrough region in said N-well region;
performing a second ion implantation with P-type conducting dopants on said substrate for a counter doping region of said N-well region and a doping region of said P-well region;
performing a third ion implantation with P-type conducting dopants on said substrate to adjust a threshold voltage of said N-well and said P-well;
performing a fourth ion implantation with N-type conducting dopants on said substrate for a counter doping region of said P-well and a doping region of said N-well region;
removing said pad oxide layer;
forming gate structures on said P-well region and said N-well region;
and
forming source/drain regions in said P-well region and said N-well region to form a NMOS device on said P-well region and a PMOS device on said N-well region.

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Dependencies are inferred from the claim text.