US 5,963,780 AGranted

Method for detecting defect sizes in polysilicon and source-drain semiconductor devices

AssigneeAdvanced Micro Devices, Inc.

InventorsZhi-Min Ling, Yung-Tao Lin, Ying Shiau

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Abstract

An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects. A second embodiment selectively silicides exposed portions of a source-drain resistor, thereby enabling testing for defects in a source-drain layer of a metal oxide semiconductor. Defect sizes are determined by comparing the measured resistance values with predetermined width and spacings of the strips.

Claims10

Dependent claims

A method for forming a semiconductor structure on a semiconductor substrate for detecting short circuits and open circuits due to defects on the semiconductor, the semiconductor having a silicon substrate, the method comprising the steps of:

forming an oxide layer on said silicon substrate;
forming an implant mask on said oxide layer, said implant mask defining a first prescribed region;
implanting said first prescribed region with a dopant to form a silicon resistor strip;
forming an interconnect mask on said oxide layer defining second prescribed regions;
etching said oxide layer at said second regions;
depositing a polysilicon layer on said semiconductor overlying said silicon resistor strip and said oxide layer;
selectively masking said polysilicon layer at third prescribed regions such that portions of said polysilicon layer remain exposed;
etching said exposed polysilicon layer portions;
depositing a refractory metal silicide layer on said semiconductor overlying said second and third regions;
applying heat to cause said deposited refractory metal silicide to react with a portion of said silicon resistor strip exposed at said second regions and said polysilicon at said third regions to form silicide and polycide as interconnecting and low-resistivity portions, respectively.

7 more elements

Dependencies are inferred from the claim text.