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US 5,962,891 AGranted
Nonvolatile semiconductor memory device
AssigneeKabushiki Kaisha Tosbhia
InventorNorihisa Arai
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AssigneeKabushiki Kaisha Tosbhia
InventorNorihisa Arai
Estimating the term…
The semiconductor device having a multilayer gate type transistor constituting memory, comprises a P-type semiconductor substrate, a source formed by diffusing an N-type impurity on a surface of the semiconductor substrate to a first depth, an N-type drain, electrically separated from the source and formed on a surface of the semiconductor substrate, a first insulating film formed on a surface of a channel region between the source and the drain, a first gate electrode formed on a surface of the first insulating film, a second insulating film formed on a surface of the first gate electrode, and a second gate electrode on the second insulating film. The semiconductor device further comprises a source wiring region, which is connected to the source of the multilayer gate transistor and formed by diffusing the N-type impurity in the semiconductor substrate to a second depth shallower than the first depth.
A semiconductor device comprising:
A semiconductor device comprising:
A semiconductor device comprising:
Dependencies are inferred from the claim text.
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No related US applications are recorded in the indexed filing history.
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
Erasable-and-programmable rom [eprom] devices not provided for in groups h10b41/00 - h10b63/00
Electronic memory devices
Term ended 3 Oct 2016 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the invention relates to an improvement of a nonvolatile memory using a multilayer type transistor as memory cells.
2. Description of the Related Art
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention and, together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.
FIG. 1 is a plan view of a semiconductor device of the present invention;
FIGS. 2A and 2B are cross sectional views of a conventional semiconductor device for explaining the manufacturing method;
Hereinbelow, the semiconductor device and the manufacturing method thereof according to embodiments of the present invention will be described with reference to accompanying drawings.
In FIGS. 1 and 8A to 14, shown are structures of the semiconductor devices according to embodiments of the present invention serving as a two-layer gate flash EEPROM of a source erase type for explaining the steps of manufacturing the same. FIGS. 8A, 9A, 10A, 11A, 12A and 13A are the cross sectional views taken along the line a--a of the memory cell portion, which crosses a word line at a right angle. On the other hand, FIGS. 8B, 9B, 10B, 11B, 12B and 13B are the cross sectional views taken along the line b--b of the region including a cell slit, which crosses a word line at a right angle. FIG. 14 is a magnified view of a portion 115 of FIG. 13A.
On the surface of a P-type semiconductor substrate 101, an oxide film 103 for element separation (600 .mu.m-thick) and a field P-layer 102 are formed by the LOCOS (local oxidation of silicon) method. After a first gate insulating film 104 (tunnel gate oxide film) of 10 nm-thick is formed by thermal oxidation on the semiconductor substrate, a polycrystalline silicon 105 serving as a floating gate electrode is deposited to 100 nm by the LPCVD method. Then, phosphorus is doped by the POCl.sub.4 method so as to be contained at an impurity surface concentration of 1.times.10.sup.20 /cm.sup.3.