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AssigneeSharp Kabushiki Kaisha
InventorsYoshimitsu Yamauchi, Masanori Yoshimi, Shinichi Sato, Keizo Sakiyama
Estimating the term…
In the nonvolatile semiconductor memory including a memory cell array having memory cells arranged in a matrix of the present invention, the memory cell array includes: a semiconductor substrate; a tunnel oxide film formed on the semiconductor substrate; floating gates formed on the tunnel oxide film; first insulating films formed on the floating gates; and control gates formed on the first insulating films, wherein each of the floating gates includes a first polysilicon film and second polysilicon films, the second polysilicon films being formed on both sides of the first polysilicon film, second insulating films are formed on the tunnel oxide film between the first polysilicon films, the second insulating films having a predetermined thickness which is thinner than that of the first polysilicon films, and the second polysilicon films are formed on the second insulating films.
A nonvolatile semiconductor memory including a memory cell array having memory cells arranged in a matrix, the memory cell array comprising:
A nonvolatile semiconductor memory including a memory cell array having memory cells arranged in a matrix, the memory cell comprising:
A nonvolatile semiconductor memory including a memory cell array having memory cells arranged in a matrix, the memory cell comprising:
Dependencies are inferred from the claim text.
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No related US applications are recorded in the indexed filing history.
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
Erasable-and-programmable rom [eprom] devices not provided for in groups h10b41/00 - h10b63/00
Floating-gate IGFETs: characterised by the shapes, relative sizes or dispositions of the floating gate electrode
Electronic memory devices
Term ended 31 Jul 2016 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory having floating gates and a method for fabricating such a nonvolatile semiconductor memory.
2. Description of the Related Art
FIG. 1A is a plan view illustrating a first step of the fabrication process of a conventional flash memory. FIGS. 1B and 1C are sectional views taken along lines B--B and C--C of FIG. 1A, respectively.
FIG. 2A is a plan view illustrating a second step of the fabrication process of the conventional flash memory. FIGS. 2B and 2C are sectional views taken along lines B--B and C--C of FIG. 2A, respectively.
FIG. 3A is a plan view illustrating a third step of the fabrication process of the conventional flash memory. FIGS. 3B and 3C are sectional views taken along lines B--B and C--C of FIG. 3A, respectively.
The present invention will be described by way of examples with reference to the accompanied drawings.
First, the configuration of a flash memory of a virtual ground architecture will be described.
In the following examples, a nonvolatile semiconductor memory of a virtual ground architecture is used where source lines (ground lines) and drain lines are not fixed but switched appropriately therebetween. As an example of the memory of the virtual ground architecture, the configuration shown in FIGS. 4A to 4C has been proposed. FIG. 4A is a plan view of a memory cell array 100 of a flash memory of the virtual ground architecture. FIGS. 4B and 4C are sectional views taken along lines B--B and C--C of FIG. 4A, respectively.