Well structure non-volatile memory device and method for fabricating the same

Abstract

In a semiconductor memory device, a plurality of first and second impurity regions of a second conductivity type are provided as wells in a semiconductor substrate of a first conductivity type. Outside of the first and second impurity regions, a plurality of third impurity regions of the first conductivity type are provided as wells in the substrate. A plurality of fourth impurity regions of the first conductivity type are provided as wells in the plurality of first impurity regions of the second conductivity type. The first impurity regions of the second conductivity type each have an impurity concentration which gradually decrease with increasing depth below the top surface of the semiconductor substrate, and the fourth impurity regions of the first conductivity type have at least two impurity concentration peaks below the top surface of the semiconductor substrate. A memory cell can be reliably erased by forming a retrograde pocket well for a memory cell array, and a diffusion well surrounding the pocket well, thus maintaining a high breakdown voltage between the pocket well and the substrate.

Dependencies are inferred from the claim text.