Super self-aligned bipolar transistor

#The present invention relates to a super self-aligned bipolar transistor and, more particularly, to a super self-aligned heterojunction bipolar transistor manufactured through the use of a selective collector epitaxial growth process.

#In general, operating speed becomes faster as a homojunction bipolar transistor size decreases. However, since an impurity concentration between emitter and base should be increased, enhancement of characteristics of the transistor based on a structure of such element is a difficult task.

#There have been proposed heterojunction bipolar transistors to cope with the above disadvantage.

#The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments, when taken in conjunction with the accompanying drawings, in which:

#FIG. 1 shows a cross-sectional view of a prior art super self-aligned npn Si/SiGe heterojunction bipolar transistor which utilizes a selective base epitaxial growth method;

#FIG. 2 offers a cross-sectional view of a heterojunction bipolar transistor which is self-aligned between the collector and base by using another prior art method previously described, after the growth of a base thin 15 film;

#FIG. 3 shows a cross-sectional view of a super selfaligned bipolar transistor formed of a selective collector growth method in accordance with a preferred embodiment the present invention.

#In FIG. 3, a buried collector 2 is first formed on a semiconductor substrate 1, and then a first oxide film 3 and a conducting thin film 4 for a base electrode are sequentially formed thereon. Then, the semiconductor substrate 1 is preferably composed of single silicon substrate, a heterojuction substrate being made of Si/ SiGe/Ge, or a heterojuction substrate being made of Si/diamond/Si or Ge. Also, the conducting thin film 4 is generally formed of polysilicon of high concentration.

#Then, a collector layer 8 is formed at an active region of transistor defined by patterning the conducting thin film 4 and the first oxide film 3, and a first spacer is formed at both sidewalls of the conducting thin film 4 surrounding the collector layer 8. Preferably, the first spacer is formed by a double layer with a different etching rate to thereby improve the reliability of the transistor, such as silicon nitride film 6 and silicon oxide film 7.