Abatement of electron beam charging distortion during dimensional measurements of integrated circuit patterns with scanning electron microscopy by the utilization of specially designed test structures

A test device comprising:

• a test region on a silicon substrate designated for said device;
• a dopant reinforcement layer in the surface of said test region;
• a first insulative layer over said test region;
• a first conductive layer over said first insulative layer;
• a first opening in said first conductive layer and said first insulative layer exposing a portion of said silicon substrate said first opening being dimensionally equivalent to corresponding openings in integrated circuit dice located elsewhere on said silicon substrate;
• a first conductive stripe formed over and patterned with said first conductive layer and which is in ohmic contact with said portion of silicon exposed through said first opening, said first conductive stripe having a width corresponding to the width of a conductive stripe on said integrated circuit dice;
• and
• a contact area on the back side of said silicon substrate whereby a continuous ohmic conductive path is provided entirely within said silicon substrate between said first conductive stripe and said contact area.

A grounded SEM inspection and measurement device comprising:

• a test region on a silicon substrate designated for said device;
• an insulative layer over said test region;
• and
• a conductive pattern over said insulative layer, said conductive pattern having a first portion containing features which are to be measured and inspected and a second portion, at least between about 10 to 100 times larger in area than said first portion, attached to said first portion constituting a ballast for the accumulation of charge;
• and
• a contact area on the back side of said silicon substrate.