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US 5,945,713 AGranted
Electrostatic discharge protection circuits for mixed voltage interface and multi-rail disconnected power grid applications
AssigneeInternational Business Machines Corporation
InventorSteven Howard Voldman
Life of this patent
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Abstract
On-chip ESD protection for semiconductor chips with mixed-voltage interface applications and internal multiple power bus architecture are described. ESD robustness in shallow trench isolation 0.50- and 0.25-micron channel-length CMOS technologies is presented in the form of ESD structures and circuits including hybrid three-rail and mixed voltage interface embodiments.
Claims4
A semiconductor chip comprising:
- a substrate;
- a first power supply rail connected to ground for off-chip drivers, a second power supply rail connected to circuit ground, and a third power supply rail connected to Vdd;
- a pad;
- and
- an ESD protect circuit comprising a first well biased through an FET so that said ESD circuit is not forward biased during normal operation when the voltage on said pad rises above a rail voltage.
2 more elements
Dependencies are inferred from the claim text.