Loading patent…
AssigneesSharp Microelectronics Technology, Inc., Sharp Kabushiki Kaisha
InventorSheng Teng Hsu
Estimating the term…
The invention provides an improved technique for forming a MOS transistor having lightly doped source and drain junction regions and low parasitic capacitance. The transistor includes raised source and drain electrodes which are strapped to the substrate adjacent the gate insulation. The raised electrodes include interconnect portions which overlie the field oxide separating the semiconductor substrate into a plurality of active regions. The source and drain electrodes are thickest where each overlies its junction with the substrate in order to control the depth of penetration of doping impurities into the substrate. After doping the electrodes, a rapid thermal anneal is performed which diffuses the doping impurities throughout the electrodes and into thin junction regions of the substrate, immediately beneath the source and drain electrodes. The thickness of the junction regions and the impurity concentration in each region is determined by the length of the diffusion anneal and the thickness of the overlying electrode. Lightly doped junction regions are formed in the substrate, between the source/drain electrodes and the channel, each junction region having a depth which is a fraction of the thickness of the overlying electrode strap, based on the substantially lower rate of impurity diffusion through single crystal silicon versus polycrystalline silicon. The thin, lightly-doped junction regions increase the breakdown voltage of the device.
A MOS transistor formed on a substrate including single crystal silicon in an active region of the substrate where the transistor is formed, the active region being separated by field insulation regions from other active regions on the substrate, the MOS transistor comprising:
Dependencies are inferred from the claim text.