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US 5,930,163 AGranted
Semiconductor memory device having two P-well layout structure
AssigneeKabushiki Kaisha Toshiba
InventorsHiroyuki Hara, Masataka Matsui
Life of this patent
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Abstract
This invention relates to P- and N-well regions where inverters constituting an SRAM cell are formed. The P-well region is divided into two parts, which are laid out on the two sides of the N-well region. Boundaries (BL11, BL12) are formed to run parallel to bit lines (BL, /BL). With this layout, diffusion layers (ND1, ND2) within the P-well regions can be formed into simple shapes free from any bent portion, reducing the cell area.
Claims13
A semiconductor memory device comprising:
- a first inverter including a first N-channel MOS transistor and a first P-channel MOS transistor;
- a second inverter including a second N-channel MOS transistor and a second P-channel MOS transistor, and having an input terminal connected to an output terminal of said first inverter and an output terminal connected to an input terminal of said first inverter;
- a third N-channel MOS transistor having a source connected to the output terminal of said first inverter, a drain connected to a first bit line, and a gate connected to a word line;
- and
- a fourth N-channel MOS transistor having a source connected to an output terminal of said second inverter, a drain connected to a second bit line, and a gate connected to said word line,
- wherein a layout direction of a source and drain of each of said first, second, third, and fourth N-channel MOS transistors and said first and second P-channel MOS transistors is set parallel to a boundary between a P-well region where said first, second, third, and fourth N-channel MOS transistors are formed, and an N-well region where said first and second P-channel MOS transistors are formed.
3 more elements
A semiconductor memory device comprising:
- a first inverter including a first N-channel MOS transistor and a first P-channel MOS transistor;
- a second inverter including a second N-channel MOS transistor and a second P-channel MOS transistor, and having an input terminal connected to an output terminal of said first inverter and an output terminal connected to an input terminal of said first inverter;
- a third P-channel MOS transistor having a drain connected to the output terminal of said first inverter, a source connected to a first bit line, and a gate connected to a word line;
- and
- a fourth P-channel MOS transistor having a drain connected to an output terminal of said second inverter, a source connected to a second bit line, and a gate connected to said word line,
- wherein a layout direction of a source and drain of each of said first and second N-channel MOS transistors and said first, second, third, and fourth P-channel MOS transistors is set parallel to a boundary between a P-well region where said first and second N-channel MOS transistors are formed, and an N-well region where said first, second, third, and fourth P-channel MOS transistors are formed.
3 more elements
Dependencies are inferred from the claim text.