Method for manufacturing a CMOS self-aligned strapped interconnection
AssigneesSharp Microelectronics Technology, Inc., Sharp Kabushiki Kaisha
InventorSheng Teng Hsu
Life of this patent
Estimating the term…
Abstract
An CMOS interconnection method that permits small source/drain surface areas has been provided. The interconnection is applicable to both strap and via type connections. The surface areas of the small source/drain regions are extended into neighboring field oxide regions by forming a silicide film from the source/drain regions to the field oxide. Interconnections on the same metal level, or to another metal level are made by contact to the silicide covered field oxide. The source/drain regions need only be large enough to accept the silicide film. Transistors with small source/drain regions have smaller drain leakage currents and less parasitic capacitance. A CMOS transistor interconnection apparatus has also been provided.
Claims19
A method for forming interconnections from at least a first transistor with source/drain regions, through surrounding field oxide regions, using gate electrode second sidewall structures, the method comprises the steps of:
- a) forming a gate electrode, with an underlying gate oxide layer and first oxide sidewalls, overlying portions of the source/drain regions;
- b) depositing a semiconductor film overlying the transistor, including the source/drain regions, the gate electrode, the first oxide sidewalls, and the surrounding field oxide regions;
- c) depositing a layer of insulator overlying the first semiconductor film;
- d) anisotropically etching the insulator deposited in Step c) to remove the insulator on the source/drain regions, gate electrode, and surrounding field oxide region, but not from the gate electrode sidewalls, whereby second sidewalls are formed;
- e) depositing a refractory metal layer overlying the semiconductor film, covering the source/drain regions and selected adjoining areas of field oxide;
- and
- f) annealing the semiconductor film deposited in Step b) and the refractory metal deposited in Step e) to form a silicide film overlying the source/drain regions and the selected adjoining areas of field oxide, whereby an electrical interconnection is made to the source/drain regions from the surrounding field oxide region to minimize the size of the source/drain regions.
A method for forming a strap interconnection from at least a second transistor with a first electrode to a first transistor with a second electrode across a field oxide region, using gate electrode second sidewall structures, the method comprises the steps of:
- a) forming gate electrodes, with underlying gate oxide layers, first oxide sidewalls, and source/drain electrodes;
- b) depositing a semiconductor film overlying the transistors, including the first and second electrodes, the first oxide sidewalls, and surrounding field oxide regions;
- c) depositing a laver of insulator overlying the semiconductor film;
- d) anisotropically etching the insulator deposited in Step c) to remove the insulator on the electrodes, and surrounding field oxide region, but not from the gate electrode sidewalls, whereby the second sidewalls are formed;
- e) depositing a refractory metal layer overlying the semiconductor film, covering the first and second electrodes and selected areas of intervening field oxide;
- and
- f) annealing the semiconductor film deposited in Step b) and the refractory metal deposited in Step e) to form a silicide film overlying the first electrode of the second transistor, the second electrode of the first transistor, and the selected areas of intervening field oxide, whereby an electrical interconnection is made to from the first transistor to the second transistor across the intervening field oxide.
A method for forming interconnections from at least a first transistor with source/drain regions, through surrounding field oxide regions, using gate electrode second sidewall structures, the method comprises the steps of:
- a) forming a gate electrode, with an underlying gate oxide layer and first oxide sidewalls, overlying portions of the source/drain regions;
- b) depositing a semiconductor film overlying the transistor, including the source/drain regions, the gate electrode, the first oxide sidewalls, and the surrounding field oxide regions;
- c) depositing a layer of insulator overlying the first semiconductor film;
- d) anisotropically etching the insulator deposited in Step c) to remove the insulator on the source/drain regions, gate electrode, and surrounding field oxide region, but not from the gate electrode sidewalls, whereby second sidewalls are formed;
- e) depositing a refractory metal layer overlying the semiconductor film, covering the source/drain regions, selected adjoining areas of field oxide, and overlying the gate electrode and second sidewalls;
- f) annealing the semiconductor film deposited in Step b) and the refractory metal deposited in Step e) to form a silicide film overlying the source/drain regions, the selected adjoining areas of field oxide, and overlying the transistor in the regions where the first semiconductor film was exposed in Step d) including the gate electrode, but not the second sidewalls;
- g) removing unreacted refractory metal overlying the second sidewalls, the second sidewalls themselves, and semiconductor film overlying the first oxide sidewalls;
- h) depositing a dielectric interlevel with a top surface overlying the transistor;
- i) etching the dielectric interlevel to form contact holes from the dielectric interlevel top surface to the silicide film overlying the selected areas of field oxide;
- and
- j) depositing metal in the contact holes to form electrical interconnects from the surface of the dielectric interlevel to the source/drain regions, whereby an electrical interconnection is made to the source/drain regions from the surrounding field oxide region to minimize the size of the source/drain regions.
Dependencies are inferred from the claim text.