Multiple clock frequency divider with fifty percent duty cycle output

A clock divider circuit comprising:

• a clock input for receiving an input clock signal;
• a clock output;
• an invert input for receiving an invert signal;
• a state machine coupled to the clock input, the clock output, and the invert input, the state machine providing an output clock signal at the clock output, the output clock signal being an odd fraction of the input clock signal and having one of a first and second phase relationship relative to the input clock signal as selected by the invert signal.

A system comprising:

• a processor operating at a first frequency, the processor comprising:
• a first clock division circuit coupled to receive a first clock signal at the first frequency and to generate a second clock signal at a second frequency which is an odd fraction of the first frequency;
• an input/output buffer coupled to exchange data using a processor output, the data being driven synchronous to the second clock signal;
• a second clock division circuit coupled to receive the first clock signal and to generate a strobe signal for the input/output buffer at the second frequency;
• and
• a memory circuit coupled to the processor and including input/output logic having an input/output port coupled to exchange data with the processor, the memory circuit being coupled to receive the second clock signal to synchronize transmission of data between the processor and the memory circuit.

A method of generating a clock signal having approximately a fifty percent duty cycle, comprising the steps of:

• receiving an input clock signal having an input clock frequency;
• selecting a phase relationship between the input clock signal and the output clock signal;
• generating a rising edge of an output clock signal from one of a rising edge or a falling edge of the input clock signal;
• generating a falling edge of the output clock signal from the other of the rising edge and the falling edge of the input clock signal through an equivalent gate delay to that through which the rising edge of the output clock signal is generated such that the output clock signal has an output clock frequency which is an odd fraction of the input clock frequency.