US 5,912,488 A · Stacked-gate flash EEPROM memory devices having mid-channel injection characteristics for high speed programming

Abstract

Flash EEPROM memory devices having mid-channel injection characteristics include a substrate having source and drain regions of first conductivity type therein extending adjacent a surface thereof. A stacked-gate electrode is also provided on the surface, between the source and drain regions. To provide improved mid-channel injection characteristics during programming, a preferred semiconductor channel region is provided in the substrate at a location extending opposite the stacked-gate electrode. This channel region comprises a first "source-side" region of second conductivity type (e.g., P+) and a second "drain-side" region of predetermined conductivity type (e.g., P-, N-). The second region has a lower first conductivity type dopant concentration therein than the drain region and a lower second conductivity type dopant concentration therein than said first region, and more preferably has a lower second conductivity type dopant concentration therein than said substrate. During programming, this EEPROM unit cell provides efficient mid-channel injection at high rates and at relatively low voltage levels and avoids many of the limitations associated with conventional stacked-gate EEPROM devices which typically provide less efficient drain-side injection and require relatively high voltage levels during programming. In particular, mid-channel injection of hot electrons from the channel region to the floating gate (within the stacked-gate electrode) is promoted by tailoring the conductivity of the channel region so that pinch-off occurs at a midpoint in the channel region during programming operations.

Claims9

Dependent claims

A flash EEPROM device, comprising:

a substrate having source and drain regions of first conductivity type semiconductor therein extending adjacent a surface thereof;
a semiconductor channel region in said substrate, said channel region containing a first region of second conductivity type semiconductor extending adjacent said source region and a second region of predetermined conductivity type semiconductor extending between said first region and said drain region, said second region having a lower first conductivity type dopant concentration therein than said drain region and a lower second conductivity type dopant concentration therein than said first region;
a control gate electrode on said substrate, opposite said semiconductor channel region;
and
a floating gate electrode disposed between said control gate electrode and said semiconductor channel region;
and
wherein said substrate comprises a bulk region of second conductivity type semiconductor extending to the surface;
wherein said source and drain regions form respective P-N junctions with said bulk region;
wherein said first region forms a non-rectifying semiconductor junction with said bulk region;
and wherein said second region has a lower second conductivity type dopant concentration therein than said bulk region.

7 more elements

Dependencies are inferred from the claim text.

Stacked-gate flash EEPROM memory devices having mid-channel injection characteristics for high speed programming

Life of this patent

Stacked-gate flash EEPROM memory devices having mid-channel injection characteristics for high speed programming

Life of this patent

Abstract

Claims9