Robust multiple word instruction and method therefor
AssigneeMicrochip Technology Incorporated
InventorsRodney J. Drake, Joseph W. Triece
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Abstract
An instruction set for a microcontroller which has robust multiple word instructions. The instruction set has a plurality of instructions wherein the plurality of instructions comprises single word instructions and multiple word instructions. At least one bit is located in a predetermined location in all non-first words of all multiple word instructions. The bit will be decoded by the microcontroller as no operation bit if the first word of the multiple word instruction is not executed prior to execution of any succeeding words in the multiple word instruction.
Claims18
An instruction set for a microcontroller which has robust multiple word instructions comprising, in combination:
- a plurality of instructions wherein said plurality of instructions are single word instructions and multiple word instructions;
- and
- at least one bit in a predetermined location in all words of a multiple word instruction after a first word of said multiple word instruction wherein said at least one bit will be decoded by said microcontroller as no operation bit if said first word of said multiple word instruction is not executed first.
A robust multiple word instruction comprising, in combination:
- an instruction having a plurality of words;
- and
- at least one bit in a predetermined location in all words of said instruction after a first word of said plurality of words wherein said at least one bit will cause said microcontroller to decode each word after said first word of said plurality of words as no operation if said first word of said plurality of words is not executed first.
A method of providing an instruction set for a microcontroller which has robust multiple word instructions comprising, in combination:
- providing a plurality of instructions wherein said plurality of instructions are single word instructions and multiple word instructions;
- and
- establishing at least one bit in a predetermined location in all words of a multiple word instruction after a first word of said multiple word instruction wherein said at least one bit will be decoded by said microcontroller as no operation bit if said first word of said multiple word instruction is not executed first.
Dependencies are inferred from the claim text.