Low resistance contact between integrated circuit metal levels and method for same

In an integrated circuit (IC) including a first metal horizontal level, a first barrier layer overlying the first metal level, a first dielectric interlevel overlying the first barrier layer, and a second barrier layer overlying the first dielectric interlevel, a method for forming sidewall barriers lining a low resistance interconnect without an intervening barrier layer between metal levels comprising the following steps:

• a) etching selected overlying areas of the first barrier layer, the first dielectric interlevel, and the second barrier layer to form a via, exposing vertical sidewall surfaces of the first dielectric interlevel and selected areas of the first metal level;
• b) conformally depositing a third barrier layer over the vertical sidewall surfaces of the first dielectric interlevel and the first metal level selected areas exposed in step a);
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• c) anisotropically etching, in the horizontal direction, to selectively remove the third barrier layer deposited over the first metal level selected areas, exposing the first metal level selected areas, but not the vertical sidewall surfaces of the first dielectric interlevel, whereby a via, having barrier surface sidewalls, is prepared to directly connect the first metal level with a subsequently deposited metal level for improved electrical conductivity.

In an integrated circuit (IC) damascene interconnection trench, having sidewall surfaces and passing through a second thickness of the dielectric interlevel, exposing selected areas of a first thickness of the dielectric interlevel overlying a metal level, a method for forming a dual damascene interconnect with sidewall barriers lining the trench and via, without forming an intervening barrier layer between the metal level and the dual damascene interconnect, the method comprising the following steps:

• a) anisotropically depositing an insulating barrier layer material overlying the trench, forming an insulating barrier layer overlying the selected areas of the dielectric interlevel first thickness where a via is subsequently formed;
• b) etching selected overlying areas of the insulating barrier layer and the underlying dielectric interlevel first thickness, exposing sidewall surfaces of the dielectric interlevel first thickness and selected areas of the metal level, whereby a via is formed from the trench to the metal level selected areas;
• c) conformally depositing a conductive barrier layer material overlying the trench and via, forming a conductive barrier layer on the sidewall surfaces of the dielectric interlevel first and second thicknesses and the metal level selected areas, whereby all the dual damascene surfaces are covered with the conductive barrier layer;
• and
• d) anisotropically etching, to selectively remove the conductive barrier layer overlying the metal level selected areas, exposing the metal level selected areas, but not the conductive barrier layer overlying the sidewall surfaces of the first dielectric interlevel first and second thicknesses, whereby a damascene process via and trench, having conductive barrier sidewall surfaces, are prepared to directly connect the metal level with a subsequently deposited copper metal level, without an intervening barrier layer, for improved conductivity.

In an integrated circuit (IC) including a first metal horizontal level, a first barrier horizontal layer overlying the first metal level, and a first dielectric interlevel overlying the first barrier layer, the first dielectric interlevel having a first thickness and second thickness overlying the first thickness, a method for forming vertical sidewall barriers lining a low resistance dual damascene interconnect between metal levels without a horizontal barrier layer intervening between the first metal level and the dual damascene interconnect comprising the following steps:

• a) etching selected areas of the first dielectric interlevel second thickness, forming a damascene interconnection trench, and exposing vertical sidewall surfaces of the first dielectric interlevel second thickness and selected horizontal surfaces of the first dielectric interlevel first thickness;
• b) anisotropically depositing, in a horizontal direction, a second barrier layer over the first dielectric interlevel, to overlie the selected horizontal surfaces of the first dielectric interlevel first thickness exposed in step a), and minimally cover the vertical sidewall surfaces of the first dielectric interlevel second thickness;
• c) etching selected overlying areas of the second barrier layer deposited in step b), selected horizontal surfaces of the first dielectric interlevel first thickness, and the first barrier layer, exposing vertical sidewall surfaces of the first dielectric interlevel first thickness and selected areas of the first metal level, whereby a via is formed from the trench to the first metal level selected areas;
• d) conformally depositing a third barrier layer over the vertical sidewall surfaces of the first dielectric interlevel second thickness exposed in step a), the second barrier layer deposited in step b), and the first metal level selected areas and vertical sidewall surfaces of the first dielectric interlevel first thickness exposed in step c);
• e) anisotropically etching, in the horizontal direction, to selectively remove the third barrier layer overlying the first metal level selected areas, exposing the first metal level selected areas, but not the third barrier layer overlying the vertical sidewall surfaces of the first dielectric interlevel first and second thicknesses, whereby a damascene process via and trench, having barrier surface sidewalls, are prepared to directly connect the first metal level with a metal subsequently deposited in the dual damascene structure for improved electrical conductivity.