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US 5,899,742 AGranted
Manufacturing method for self-aligned local interconnects and contacts simultaneously
OwnerShih-Wei Suninventor
Life of this patent
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Abstract
The invention provides a novel method, in which self-aligned, borderless contacts and local interconnections of semiconductor devices are manufactured in an integral process. The method is compatible with the LOGIC self-aligned titanium silicide (SALICIDE) and N+/P+ poly dual gate process modules. That is, this invention provides a self-aligned local-interconnect and contact (SALIC) method for a logic technology to forming the self-aligned, borderless contacts, and local interconnects (LI) simultaneously.
Claims12
A manufacturing method for self-aligned, borderless contacts and local interconnections, comprising:
- providing a substrate, wherein the substrate having a plurality of shallow trench isolation layers, the shallow trench isolation layers used for defining at least a local interconnect area and an active area;
- forming a first gate electrode and a second gate electrode respectively on the local interconnect area and the active area, wherein the first gate electrode and the second gate electrode respectively having a gate oxide layer, a polysilicon layer above the gate oxide layer, a silicide layer, and a first isolation layer;
- forming a plurality of source/drain regions in the substrate by ion implantation using the first gate electrode and the second gate electrode as masks;
- forming a first spacer and a second spacer respectively around the first gate electrode and the second gate electrode;
- etching a portion of the first gate electrode and a portion of the first spacer to expose a portion of the silicide layer of the first gate electrode;
- removing the exposed portion of the gate oxide layer;
- forming a self-aligned silicide layer on the surface of the source/drain region;
- and
- forming a second isolation layer and a dielectric layer over the shallow trench isolation layers, wherein the second isolation layer and the dielectric layer having a first opening above the local interconnect area and a second opening above the active area, wherein the first opening is used for exposing portions of the first gate electrode, the silicide layer, the first spacer, and the self-aligned silicide layer on the surface of the source/drain region around the first electrode, and the second opening is used for exposing portions of the second gate electrode, the second spacer, and the self-aligned silicide layer on the surface of the source/drain region around the second electrode, whereby the self-aligned, borderless contact and local interconnection are formed thereon.
6 more elements
A manufacturing method for self-aligned, borderless contacts and local interconnections, comprising:
- providing a substrate, wherein the substrate having a plurality of shallow trench isolation areas, the shallow trench isolation layers used for defining at least a local interconnect area and an active area;
- forming a first gate electrode and a second gate electrode respectively on the local interconnect area and the active area, wherein the first gate electrode and the second gate electrode respectively having a gate oxide layer, a polysilicon layer above the gate oxide layer, a silicide layer, and a first isolation layer;
- forming a plurality of source/drain regions in the substrate by ion implantation using the first gate electrode and the second gate electrode as masks;
- forming a first spacer and a second spacer respectively around the first gate electrode and the second gate electrode;
- etching a portion of the first gate electrode and a portion of the first spacer to expose a portion of the silicide layer of the first gate electrode;
- removing the exposed portion of the gate oxide layer;
- forming a self-aligned silicide layer on the surface of the source/drain region;
- forming a second isolation layer and a dielectric layer over the shallow trench isolation layers, wherein the second isolation layer and the dielectric layer having a first opening above the local interconnect area and a second opening above the active area, wherein the first opening is used for exposing portions of the first gate electrode, the silicide layer, the first spacer, and the self-aligned suicide layer on the surface of the source/drain region around the first electrode, and the second opening is used for exposing portions of the second gate electrode, the second spacer, and the self-aligned silicide layer on the surface of the source/drain region aroung the second electrode;
- forming a barrier/glue layer on sidewalls and bottoms of the first opening and the second opening;
- and
- forming a plug layer over the substrate to fill the first opening and the second opening.
8 more elements
Dependencies are inferred from the claim text.