Switching midplane and interconnecting system for interconnecting large numbers of signals

An electrically reconfigurable logic assembly for use in an electrically reconfigurable hardware emulation system which can be configured with a circuit design in response to the input of circuit information, said electrically reconfigurable assembly comprising:

• a midplane printed circuit board having a first face and a second face;
• a first and second electrically reconfigurable logic board mounted on said first face of said midplane printed circuit board in a first direction, each of said first and second electrically reconfigurable logic boards comprising a plurality of logic chips installed thereon, each of said logic chips having internal circuitry which can be reprogrammably configured to provide functional elements selected from the group of at least combinational logic elements and sequential logic elements;
• a switching board mounted on said second face of said midplane printed circuit board in a second direction, said second direction being substantially non-parallel to said first direction, said at least one switching board comprising a plurality of switch chips installed thereon, said switching board crossing said first and said second logic boards at a first intersection region and a second intersection region;
• a first plurality of double ended pins, said first plurality of double ended pins located within said first intersection region, passing through said midplane printed circuit board and extending from said first face and said second face, a first of said first plurality of double ended pins placing a lead of a first of said plurality of logic chips installed on said first electrically reconfigurable logic board in electrical communication with a first lead of a first of said plurality of switch chips installed on said switching board;
• a second plurality of double ended pins, said second plurality of double ended pins located within said second intersection region, passing through said midplane printed circuit board and extending from said first face and said second face, a first of said second plurality of double ended pins placing a lead of a second of said plurality of logic chips installed on said second electrically reconfigurable logic board in electrical communication with a second lead of said first of said plurality of switch chips;
• a first plurality of single ended pins, said first plurality of single ended pins located between said first and said second intersection region, each of said first plurality of single ended pins extending through said first face of said midplane printed circuit board and being in electrical communication with one of a plurality of corresponding circuit board traces;
• a second plurality of single ended pins, said second plurality of single ended pins located adjacent said first intersection region, each of said second plurality of single ended pins extending through said second face of said midplane printed circuit board and being in electrical communication with one of said corresponding circuit board traces;
• and
• one of said first plurality of single ended pins placing a lead of a third of said plurality of logic chips installed on said second electrically reconfigurable logic board in electrical communication with a third lead of said first of said plurality of switch chips.

An hierarchically interconnected hardware logic emulation apparatus comprising:

• a midplane printed-circuit board including a first face and a second face, said second face substantially parallel to said first face, and having a plurality of conductive traces disposed therein;
• a plurality of logic boards mounted substantially parallel to one another on said first face of said midplane printed-circuit board, each of said plurality of logic boards comprising:
• a plurality of reprogrammable logic chips, each of said reprogrammable logic chips having internal circuitry which can be reprogrammable configured to provide functional elements, each of said reprogrammable logic chips also having programmable input/output terminals which can be reprogrammably connected to said functional elements configured into said reprogrammable logic chips;
• each of said plurality of logic boards also comprising a first plurality of reprogrammable switch chips, each of said first plurality of reprogrammable switch chips having a first group of input/output terminals connected to said programmable input/output terminals of each of said reprogrammable logic chips and having internal circuitry which can be reprogrammable configured to provide interconnections between said first group of input/output terminals, each of said first plurality of reprogrammable switch chips also having a second group of input output terminals;
• a plurality of switching boards mounted substantially parallel to one another on said second face of said midplane printed-circuit board in a direction substantially perpendicular to said plurality of said logic boards, each of said plurality of switching boards having a second plurality or reprogrammable switch chips installed thereon, each of said plurality of switching boards crossing each of said plurality of logic boards at a plurality of intersection regions, said second plurality of reprogrammable switch chips connected to said group of input/output terminals on said first plurality of reprogrammable switch chips on each of said plurality of logic boards, whereby selected functional elements configured into selected ones of said plurality of logic chips on one of said logic boards can be reconfigurable interconnected to selected functional elements configured into selected ones of said plurality of reprogrammable logic chips one another of said plurality of logic boards;
• a plurality of double-ended pins, each of said plurality of double-ended pins extending through said intersection regions of said midplane printed-circuit board, each of said plurality of double ended pins in electrical communication with one of said plurality of logic boards and one of said plurality of switching boards;
• a plurality of first single-ended pins, each of said first single-ended pins extending from said first face of said midplane printed-circuit board, each of said plurality of first single-ended pins in electrical communication with one of said plurality of logic boards, each of said plurality of first single-ended pins in electrical contact with at least one of said plurality of conductive traces of said midplane printed-circuit board, said first single-ended pins and said plurality of double ended pins forming a plurality of rows and columns of equidistantly spaced pins on said first face of said midplane printed circuit board;
• and
• a plurality of second single-ended pins, each of said plurality of second single-ended pins extending from said second face of said midplane printed-circuit board, each of said plurality of second single-ended pins in electrical communication with one of said plurality of switching boards, each of said of plurality of second single-pine in contact with at least one of said plurality of conductive traces such that a first of said second single-ended pins is in electric contact with a first of said first single-ended pins, said second single-ended pins and said double-ended pins forming a plurality of columns of equidistantly spaced pins on said second face of said midplane printed circuit board.

An electrically reconfigurable logic assembly for use in an electrically reconfigurable hardware emulation system which can be configured with a circuit design in response to the input of circuit information, said electrically reconfigurable assembly comprising:

• a midplane printed circuit board having a first face and a second face;
• a first and second electrically reconfigurable logic board mounted on said first face of said midplane printed circuit board in a first direction, each of said first and second electrically reconfigurable logic boards comprising a plurality of logic chips installed thereon, each of said logic chips having internal circuitry which can be reprogrammably configured to provide functional elements selected from the group of at least combinational logic elements and sequential logic elements;
• a switching board mounted on said second face of said midplane printed circuit board in a second direction, said second direction being substantially non-parallel to said first direction, said at least one switching board comprising at least one switch chip installed thereon, said switching board crossing said first and said second logic boards at a first intersection region and a second intersection region;
• a first plurality of double ended pins, said first plurality of double ended pins located within said first intersection region, passing through said midplane printed circuit board and extending from said first face and said second face, a first of said first plurality of double ended pins placing a lead of a first of said plurality of logic chips installed on said first electrically reconfigurable logic board in electrical communication with a first lead on said at least one switch chip installed on said switching board;
• a second plurality of double ended pins, said second plurality of double ended pins located within said second intersection region, passing through said midplane printed circuit board and extending from said first face and said second face, a first of said second plurality of double ended pins placing a lead of a second of said plurality of logic chips installed on said second electrically reconfigurable logic board in electrical communication with a second lead of said at least one switch chip;
• a first plurality of single ended pins, said first plurality of single ended pins located between said first and said second intersection region, each of said first plurality of single ended pins extending through said first face of said midplane printed circuit board and being in electrical communication with one of a plurality of corresponding circuit board traces;
• a second plurality of single ended pins, said second plurality of single ended pins located adjacent said first intersection region, each of said second plurality of single ended pins extending through said second face of said midplane printed circuit board and being in electrical communication with one of said corresponding circuit board traces;
• and
• one of said first plurality of single ended pins placing a lead of a third of said plurality of logic chips installed on said second electrically reconfigurable logic board in electrical communication with a third lead of said at least one switch chip.

An hierarchically interconnected hardware logic emulation apparatus comprising:

• a midplane printed-circuit board including a first face and a second face, said second face substantially parallel to said first face, and having a plurality of conductive traces disposed therein;
• a plurality of logic boards mounted substantially parallel to one another on said first face of said midplane printed-circuit board, each of said plurality of logic boards comprising:
• a plurality of reprogrammable logic chips, each of said reprogrammable logic chips having internal circuitry which can be reprogrammably configured to provide functional elements, each of said reprogrammable logic chips also having programmable input/output terminals which can be reprogrammably connected to said functional elements configured into said reprogrammable logic chips;
• each of said plurality of logic boards also comprising at least one reprogrammable first switch chip, said at least one reprogrammable first switch chip having a first group of input/output terminals connected to said programmable input/output terminals of each of said reprogrammable logic chips and having internal circuitry which can be reprogrammably configured to provide interconnections between said first group of input/output terminals, said at least one reprogrammable first switch chip also having a second group of input output terminals;
• a plurality of switching boards mounted substantially parallel to one another on said second face of said midplane printed-circuit board in a direction substantially perpendicular to said plurality of said logic boards, each of said plurality of switching boards having at least one reprogrammable second switch chip installed thereon, each of said plurality of switching boards crossing each of said plurality of logic boards at a plurality of intersection regions, said at least one reprogrammable second switch chip connected to said second group of input/output terminals on said at least one reprogrammable first switch chip on each of said plurality of logic boards, whereby selected functional elements configured into selected ones of said plurality of logic chips on one of said logic boards can be reconfigurably interconnected to selected functional elements configured into selected ones of said plurality of reprogrammable logic chips on another of said plurality of logic boards;
• a plurality of double-ended pins, each of said plurality of double-ended pins extending through said intersection regions of said midplane printed-circuit board, each of said plurality of double ended pins in electrical communication with one of said plurality of logic boards and one of said plurality of switching boards;
• a plurality of first single-ended pins, each of said first single-ended pins extending from said first face of said midplane printed-circuit board, each of said plurality of first single-ended pins in electrical communication with one of said plurality of logic boards, each of said plurality of first single-ended pins in electrical contact with at least one of said plurality of conductive traces of said midplane printed-circuit board, said first single-ended pins and said plurality of double-ended pins forming a plurality of rows and columns of equidistantly spaced pins on said first face of said midplane printed circuit board;
• and
• a plurality of second single-ended pins, each of said plurality of second single-ended pins extending from said second face of said midplane printed-circuit board, each of said plurality of second single-ended pins in electrical communication with one of said plurality of switching boards, each of said plurality of second single-ended pins in contact with at least one of said plurality of conductive traces such that a first of said second single-ended pins is in electric contact with a first of said first single-ended pins, said second single-ended pins and said double-ended pins forming a plurality of columns of equidistantly spaced pins on said second face of said midplane printed circuit board.