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US 5,877,642 AGranted
Latch circuit for receiving small amplitude signals
AssigneeNEC Corporation
InventorHiroyuki Takahashi
Life of this patent
Estimating the term…
Abstract
The latch circuit having an input stage supplied with an input signal and, when activated, producing an output signal responsive to the input signal, and an latching stage coupled to the input stage and, when activated, holding a level of the output signal, the input stage including a pair of bipolar transistors Q1, Q2 coupled in a differential form, the latching stage including a pair of insulated gate field effect transistors M1, M2 coupled in a differential form.
Claims5
A semiconductor circuit comprising:
- a first bipolar transistor connected between a first node and a second node and having a base connected to a first input terminal;
- a second bipolar transistor connected between a third node and said second node and having a base connected to a second input terminal;
- a first resistive element connected between a first power supply line and said first node;
- a second resistive element connected between said first power supply line and said third node;
- a first MOS transistor connected between said first node and a fourth node and having a gate;
- a second MOS transistor connected between said third node and said fourth node and having a gate;
- a first current source connected to said second node and operating during a first period of time;
- a second current source connected to said fourth node and operating during a second period of time;
- a first signal transfer circuit coupled between said first node and the gate of said second MOS transistor;
- and
- a second signal transfer circuit coupled between said third node and the gate of said first MOS transistor.
8 more elements
Dependencies are inferred from the claim text.