US 5,864,164 AGranted

Multi-stage ROM structure and method for fabricating the same

AssigneeUnited Microelectronics Corp.

InventorJemmy Wen

Life of this patent

Estimating the term…

Loading patent…

Abstract

A multi-stage read only memory (ROM) device and a method for fabricating the same. The device includes a source/drain pole and a gate in a trench, wherein the gate intersects the source/drain pole at an angle to form a number of memory cells. The fabrication of the multi-stage ROM includes two encoding processes. The first encoding process includes implantation of impurity ions in a portion of memory cells to adjust the threshold voltage, so that some of the memory cells have a first threshold voltage and the others have a second threshold voltage. The second encoding process includes forming a number of dielectric remainders at the bottom of the gate trench of a portion of the memory cells, so that some of the memory cells have a first effective channel width and the others have a second effective channel width. As a result, the memory cells of a ROM are of four types with different combinations of threshold voltages and effective channel widths.

Claims10

Dependent claims

A multi-stage read only memory device, comprising:

a substrate;
a plurality of mutually parallel first trenches in the substrate, extending in a first direction;
a plurality of mutually parallel second trenches in the substrate, extending in a second direction, wherein the second trenches have a depth which is shallower than a depth of the first trenches, and wherein the first direction intersects the second direction at a predetermined angle;
a plurality of source/drain poles, wherein each of the source/drain poles is within a respective one of the first trenches and coupled to a bit line;
a plurality of impurity diffusion regions, distributed on opposite side-walls and at the bottom of one of the second trenches;
a plurality of dielectric remainders, respectively distributed at the bottom of a respective one of the second trenches;
an oxide layer on a periphery and bottom of the second trenches;
and
a plurality of gates, wherein each of the gates is within a respective one of the second trenches over the oxide layer and coupled to a word line, the gates and the source/drain poles forming a plurality of memory cells, and a portion of the substrate adjacent to the oxide layer forming a channel of two adjacent source/drain poles.

6 more elements

Dependencies are inferred from the claim text.