Two transistor flash EEprom cell and method of operating same

Abstract

A flash electrically erasable programmable read only memory (EEPROM) cell fabricated in a semiconductor substrate. A first well region having a first conductivity type is located in the semiconductor substrate. A second well region having a second conductivity type, opposite the first conductivity type, is located in the first well region. A non-volatile memory transistor and an independently controllable access transistor are fabricated in the second well region. The non-volatile memory transistor and the access transistor are connected in series, such that the source of the access transistor is coupled to the drain of the non-volatile memory transistor. The first well region, the second well region, the non-volatile memory transistor and the access transistor are biased such that electrons are transferred from the first well region to a floating gate of the non-volatile memory transistor by Fowler-Nordheim tunneling during an erase mode, and electrons are transferred from the floating gate of the non-volatile memory transistor through the access transistor by Fowler-Nordheim tunneling during a program mode. None of the biasing voltages exceed 12 Volts, thereby enabling the flash EEPROM cell to operate in a 3.3 Volt system. In one embodiment, an array of flash EEPROM cells are fabricated in the second well region.

Dependencies are inferred from the claim text.