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US 5,861,656 AGranted
High voltage integrated circuit
AssigneeTelefonaktiebolaget LM Ericsson
InventorImre Keri
Life of this patent
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Abstract
The invention relates to a high voltage integrated circuit with connecting metal conductors (30, 32) connected to ground or potential near ground and covered by a passivating layer (18). The invention is characterized by said passivating layer (18) being partially broken up above said metal conductors to prevent activation of parasitic MOS-transistor.
Claims8
A high voltage integrated circuit comprising:
- a substrate biased at a first potential;
- and
- interconnecting metal conductors biased at a second potential different from said first potential disposed on said substrate and partially covered by a passivating layer so as to prevent activation of parasitic MOS-transistors.
A high voltage integrated circuit comprising:
- a semiconductor substrate biased at a first potential;
- a metallization pattern formed on said semiconductor substrate and including a plurality of narrow, elongated metal lines;
- a terminal provided external to said high voltage integrated circuit held at a second potential different from said first potential and electrically connected to at least one of said elongated metal lines;
- and
- a passivation layer provided over said metallization layer and at least partially broken up along a length of said at least one of said elongated metal lines in such a manner that said at least one of said elongated metal lines traps charge carriers.
2 more elements
An integrated circuit comprising:
- a substrate biased at a first potential;
- and
- means for preventing activation of parasitic transistors in said substrate including a plurality of elongated interconnecting conductors disposed on said substrate and held at a second potential.
Dependencies are inferred from the claim text.