Integrated circuit memory devices having improved supply line connections, and methods of forming same

Abstract

Integrated circuit memory devices having improved supply line connections utilize preexisting semiconductor regions (e.g., N-type well regions) in a semiconductor substrate as interconnect regions between thin polysilicon supply lines and metal supply lines. A semiconductor substrate is provided having a region of first conductivity type semiconductor therein extending to a face thereof. This region of first conductivity type may be formed in a peripheral circuit portion of the substrate. A memory device, such as an SRAM device, is also preferably provided adjacent the face of the substrate, in a memory cell portion of the substrate. The memory device contains at least one polysilicon load element therein having a first resistivity. A polysilicon supply line is also electrically connected in series between the polysilicon load element and the region of first conductivity type. The polysilicon supply line is preferably formed as an extension of the polysilicon load element but is doped more heavily with an impurity of predetermined conductivity type so that it has a second resistivity which is less than the first resistivity. In addition, a metal supply line is electrically connected to the region of first conductivity type so that an indirect electrical connection is made between the polysilicon supply line and the metal supply line. Accordingly, a preexisting semiconductor region in the substrate may be utilized as an interconnect region to reliably electrically interconnect supply lines having reduced thicknesses.

Dependencies are inferred from the claim text.