Multiple transistor integrated circuit with thick copper interconnect

A multiple transistor integrated circuit with a thick metal interconnect structure;

• comprising:
• a plurality of gate bond pads, each for receiving a gate input to a respective LDMOS transistor;
• a plurality of source bond pads, each for receiving a source input to a respective LDMOS transistor, all coupled together and to a common source buss;
• a plurality of columns of multiple rows of diffusion regions, said diffusion regions alternating and being of a first and a second conductivity type;
• first level metal layers fabricated over and electrically contacting each of said diffusion regions, said first level metal layers forming source stripes and drain stripes;
• a plurality of columnar second level metal source busses, each coupled to said common source buss and each partially overlying a respective one of said plurality of columns of multiple rows of diffusions, each columnar second level metal source buss being coupled to selected ones of said source stripes;
• a plurality of columnar second level metal drain busses, each coupled to a respective one of said drain bond pads, each partially overlying a respective one of said plurality of columns of multiple rows of diffusions and each being spaced apart from said plurality of columnar second level metal source busses, said source and drain busses being alternating columnar busses;
• a plurality of third level thick metal source shorting busses comprised of a metal having a greater conductivity than the metals of said first level metal layers and second level metal source busses, each associated with and partially overlying a respective one of said source busses;
• and
• a plurality of third level thick metal drain shorting busses comprised of a metal having a conductivity that is greater than the conductivity of said first level metal layers and second level drain busses, each associated with and partially overlying a respective one of said drain busses;
• the third level thick metal source and drain shorting busses being in electrical contact with said source and drain busses and lowering the on resistance of the LDMOS transistors on the integrated circuit.