Semiconductor memory having storage capacitor connected to diffusion region through barrier layer
AssigneeNEC Corporation
InventorKaoru Narita
Life of this patent
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Abstract
A memory cell comprising a MOSFET formed on a principle surface of a semiconductor substrate and an information storage capacitor having a storage electrode formed in or on the substrate so as to contact with a drain region of the MOSFET, and a capacitor electrode formed adjacent to the storage electrode with a capacitor insulator film being sandwiched between the storage electrode and the capacitor electrode. The storage electrode is connected to the drain region of the MOSFET through a thin barrier layer which is formed between the drain region and the storage electrode region so as to prevent impurities in the storage electrode from being diffused into the drain region.
Claims4
A memory cell comprising:
- a semiconductor substrate;
- a MOSFET including first and second diffusion regions which are formed in a principal surface of said semiconductor substrate, separately from each other so as to form a channel between said first and second diffusion regions, said MOSFET also including an oxide layer formed to cover said principal surface of said semiconductor substrate above said channel, and a gate electrode formed on said oxide layer above said channel;
- and
- a capacitor having a storage electrode formed to contact with said first diffusion region, and a capacitor electrode formed on said storage electrode with a capacitor insulator film being sandwiched between said storage electrode and said capacitor electrode, said storage electrode being formed of an impurity doped polysilicon, said storage electrode being spaced from and connected to said first diffusion region by a thin barrier layer which is formed between said first diffusion region and said storage electrode, said thin barrier layer being formed of a single thin film composed of a material selected from the group consisting of silicon nitride and silicon oxide, said thin barrier layer not only preventing impurities in said impurity doped polysilicon of said storage electrode from being diffused into said semiconductor substrate, but also ensuring electrical connection between said first diffusion region and said storage electrode.
Dependencies are inferred from the claim text.