Heterojunction bipolar transistor having heterostructure ballasting emitter

A multi-finger HBT device comprising:

• a plurality of heterojunction bipolar transistors, said heterojunction bipolar transistor comprising
• a semi-insulating substrate;
• a subcollector layer on said semi-insulating substrate;
• a collector layer on said subcollector layer, said collector layer being comprised of n.sup.- -GaAs;
• a base layer on said collector layer, said base layer being comprised of p.sup.+ -GaAs;
• a heterostructure emitter having a n-type setback layer and a wide-gap ballasting emitter layer, said emitter setback layer being on said base layer, and said ballasting emitter layer being on said emitter setback layer,
• wherein said emitter setback layer is comprised of n-Al.sub.x Ga.sub.1-x As with 0.ltoreq.x.ltoreq.0.2, and said ballasting emitter layer is comprised of n-Al.sub.y Ga.sub.1-y As with 0.25.ltoreq.y.ltoreq.1;
• and
• an emitter cap layer on said ballasting emitter layer,
• wherein said heterostructure emitter has a larger width than said emitter cap layer such that a depleted passivation ledge is formed;
• and
• means for interconnecting said collector layer, said base layer, and said emitter of each heterojunction bipolar transistor respectively.

A multi-finger HBT device comprising:

• a plurality of heterojunction bipolar transistors, said heterojunction bipolar transistor comprising
• a semi-insulating substrate;
• a subcollector layer on said semi-insulating substrate;
• a collector layer on said subcollector layer, said collector layer being comprised of lightly doped n-SiC;
• a base layer on said collector layer, said base layer being comprised of heavily doped p-SiC;
• a heterostructure emitter having a n-type setback layer and a wide-gap ballasting emitter layer, said emitter setback layer being on said base layer, and said ballasting emitter layer being on said emitter setback layer,
• wherein said emitter setback layer is comprised of n-SiC, and said ballasting emitter layer is comprised of heavily doped n-GaN;
• and
• an emitter cap layer on said ballasting emitter layer,
• wherein said heterostructure emitter has a larger width than said emitter cap layer such that a depleted passivation ledge is formed;
• and
• means for interconnecting said collector layer, said base layer, and said emitter of each heterojunction bipolar transistor respectively.