In-situ low wafer temperature oxidized gas plasma surface treatment process

A method of forming an interlevel dielectric layer without peeling or cracking in the fabrication of an integrated circuit device comprising:

• providing semiconductor device structures in and on a semiconductor substrate;
• providing an insulating layer overlying said semiconductor device structures and a first conducting layer overlying said insulating layer and extending down through said insulating layer to contact one of said semiconductor device structures;
• depositing a first dielectric layer overlying said first conducting layer;
• coating a spin-on-glass layer over said first dielectric layer;
• etching back said spin-on-glass layer wherein a polymer buildup is formed on said spin-on-glass layer;
• and
• in a deposition chamber, first treating said spin-on-glass layer with an oxygen plasma treatment at a first temperature of between about 50.degree. and 250.degree. C. wherein said treatment removes said polymer buildup and thereby prevents cracking and peeling of said spin-on-glass layer and thereafter depositing a second dielectric layer overlying said spin-on-glass layer at a second temperature of about 400.degree. C. to complete said interlevel dielectric layer in said fabrication of said integrated circuit device.

A method of forming an interlevel dielectric layer without peeling or cracking in the fabrication of an integrated circuit device comprising:

• providing semiconductor device structures in and on a semiconductor substrate;
• providing an insulating layer overlying said semiconductor device structures and a first conducting layer overlying said insulating layer and extending down through said insulating layer to contact one of said semiconductor device structures;
• depositing a first dielectric layer overlying said first conducting layer;
• coating a spin-on-glass layer over said first dielectric layer;
• etching back said spin-on-glass layer wherein a polymer is formed on said spin-on-glass layer;
• in a deposition chamber, first treating said spin-on-glass layer with an oxygen plasma treatment comprising flowing O.sub.2 gas at between about 100 and 5000 sccm at a temperature of between about 50.degree. and 250.degree. C. for between about 2 to 10 seconds wherein said treatment removes said polymer and thereby prevents cracking and peeling of said spin-on-glass layer and thereafter depositing a TEOS layer overlying said spin-on-glass layer at a temperature of about 400.degree. C. to complete said interlevel dielectric layer;
• etching a via opening through said interlevel dielectric layer to said first conducting layer;
• and
• depositing and patterning a second conducting layer within said via opening to complete said fabrication of said integrated circuit device.