Integrated circuits with borderless vias

A method of forming interconnecting layers in a semiconductor device over a foundation layer, the foundation layer including a dielectric layer having at least one trench formed therein, the at least one trench being filled with a plug material, and the foundation layer further including a barrier layer formed atop the foundation layer, the method comprising the steps of:

• a) forming a metal layer on the surface of the barrier layer;
• b) forming a protection layer on the surface of the metal layer;
• c) patterning the protection layer and the metal layer to define a line of composite protection/metal on the surface of the barrier layer;
• d) forming an etch stop layer which substantially conforms to the shape of the line of composite protection/metal on the surface of the barrier layer;
• e) removing selected portions of the etch stop layer to expose the protection surface of the composite protection/metal line and portions of the barrier layer while leaving etch stop spacers conforming to at least one sidewall portion of the line;
• f) removing portions of the barrier layer between the etch stop spacers;
• g) forming a layer of via dielectric that covers, and extends above, the line;
• h) removing a portion of the via dielectric layer above the composite protection/metal line to expose a portion of the protection surface of the composite protection/metal line;
• and
• i) removing a portion of the protection surface from the composite protection/metal line, to expose the metal portion of the line, wherein step h) includes applying an etch chemistry to the via dielectric, the etch chemistry characterized by an etch stop spacers to via dielectric selectivity greater than one, and wherein step i) includes applying an etch chemistry to the protection layer, the etch chemistry characterized by an etch stop spacers to protection layer selectivity greater than one.