US 5,858,852 A · Fabrication process of a stack type semiconductor capacitive element

Abstract

At first, a silicon oxide layer is selectively formed on the surface of a semiconductor substrate. Next, a first amorphous silicon film doped with phosphorous in the concentration of about 1.times.10.sup.20 (atoms/cm.sup.3) and a non-doped second amorphous silicon film are deposited in sequential order. By this, an amorphous silicon layer for lower electrode constituted of the first and second amorphous silicon films is formed. Then, an HSG (unevenness) is formed on the surface of the amorphous silicon layer for lower electrode. Subsequently, the amorphous silicon layer for lower electrode is patterned to form a lower electrode of the stack type capacitive element. Thereafter, a capacitance insulation layer is formed on the upper surface and the side surface of the lower electrode. Then, over the entire surface, an upper electrode is deposited.

Claims22

Dependent claims

A fabrication process for forming a stack type semiconductor capacitive element, comprising the steps of:

selectively forming an insulation layer on the surface of a semiconductor substrate for defining an element region;
forming a first amorphous silicon film with an impurity concentration greater than or equal to 1.times.10.sup.20 (atoms/cm.sup.3) on said element region;
forming a second amorphous silicon film with an impurity concentration less than or equal to 1.times.10.sup.18 (atoms/cm.sup.3) on said first amorphous silicon film, said second amorphous silicon film and said first amorphous silicon film constituting an amorphous silicon layer for lower electrode;
and
forming unevenness on the surface of said amorphous silicon layer for lower electrode by a heat treatment.

2 more elements

A fabrication process for forming a stack type semiconductor capacitive element, comprising the steps of:

selectively forming an insulation layer on the surface of a semiconductor substrate for defining an element region;
forming a first amorphous silicon film with an impurity concentration greater than or equal to 1.times.10.sup.20 (atoms/cm.sup.3) on said element region;
forming a second amorphous silicon film with an impurity concentration less than or equal to 1.times.10.sup.18 (atoms/cm.sup.3) on said first amorphous silicon film, said second amorphous silicon film and said first amorphous silicon film constituting an amorphous silicon layer for lower electrode;
patterning said amorphous silicon layer for lower electrode to form a patterned amorphous silicon layer;
forming a side wall of amorphous silicon with an impurity concentration less than or equal to 1.times.10.sup.18 (atoms/cm.sup.3) on the side surface of said patterned amorphous silicon layer;
and
forming unevenness on the surfaces of said patterned amorphous silicon layer and said side wall by heat treatment and whereby forming a lower electrode having patterned amorphous silicon layer and said side wall with said unevenness.

4 more elements

Dependencies are inferred from the claim text.

Fabrication process of a stack type semiconductor capacitive element

Life of this patent

Fabrication process of a stack type semiconductor capacitive element

Life of this patent

Abstract

Claims22