Salicide integration method

A method of fabricating an integrated circuit device comprising:

• growing a layer of gate silicon oxide over the surface of a semiconductor substrate;
• depositing a polysilicon layer overlying said gate silicon oxide layer;
• etching away said polysilicon and said gate oxide layers where they are not covered by a mask to form a gate electrode;
• implanting first BF.sub.2 ions to form lightly doped regions within said semiconductor substrate using said gate electrode as a mask;
• depositing a dielectric layer overlying said semiconductor substrate and said gate electrode;
• anisotropically etching said dielectric layer to leave spacers on the sidewalls of said gate electrode;
• implanting second BF.sub.2 ions to form P+ source and drain regions within said semiconductor substrate using said gate electrode and said spacers as a mask;
• conformally depositing a layer of titanium over the surfaces of said semiconductor substrate;
• implanting arsenic ions into said titanium layer;
• first annealing said semiconductor substrate whereby said titanium layer is transformed into a titanium silicide layer except where said titanium layer overlies said spacers and whereby said arsenic ions stuff the grain boundaries of said titanium silicide layer thereby preventing diffusion of silicon from said titanium silicide layer into said titanium layer overlying said spacers;
• stripping said titanium layer overlying said spacers to leave said titanium silicide layer only on the top surface of said gate electrode and on the top surface of said semiconductor substrate overlying said source and drain regions;
• second annealing said semiconductor substrate whereby said titanium silicide layer has lower resistance;
• depositing an insulating layer over the surface of said semiconductor substrate covering said gate electrode;
• and
• providing metallization with electrical connections to complete the fabrication of said integrated circuit device.

A method of fabricating an integrated circuit device comprising:

• providing a polysilicon gate electrode on a semiconductor substrate and associated source and drain regions within said semiconductor substrate wherein spacers are formed on the sidewalls of said gate electrode;
• conformally depositing a layer of titanium over said gate electrode, said spacers and said source and drain regions within said semiconductor substrate;
• implanting arsenic ions into said titanium layer;
• first annealing said semiconductor substrate whereby said titanium layer overlying said gate electrode and said semiconductor substrate is transformed into a titanium silicide layer and wherein said arsenic ions within said titanium layer stuff the grain boundaries of said titanium layer whereby titanium silicon does not form overlying said spacers and whereby said arsenic ions stuff the grain boundaries of said titanium silicide layer thereby preventing diffusion of silicon from said titanium silicide layer into said titanium layer overlying said spacers;
• stripping said titanium layer overlying said spacers;
• second annealing said semiconductor substrate whereby the resistance of said titanium silicide layer is decreased;
• depositing an insulating layer over the surface of said semiconductor substrate covering said gate electrode;
• and
• providing metallization with electrical connections to complete the fabrication of said integrated circuit device.