Methods for manufacturing integrated circuit memory devices including trench buried bit lines

A memory device manufacturing method comprising the steps of:

• forming a device isolation film which defines an active region and a device isolation region in an integrated circuit substrate;
• forming a transistor having spaced apart drain and source regions and a gate electrode therebetween, within said active region;
• forming an interlayer insulating film on said transistor;
• forming a plurality of first contact holes which expose said source and drain regions of said transistor, by patterning said interlayer insulating film;
• forming a pad conductive layer in said first contact holes;
• forming a plurality of trenches by partially etching said pad conductive layer and interlayer insulating film;
• forming a first insulating layer on the pad conductive layer and on the interlayer insulating film, and lining the trenches;
• forming a second contact hole which partially exposes the surface of said trenches formed on said drain region of said transistor, by partially etching said first insulating layer;
• forming a bit line which is electrically connected to said pad conductive layer and said drain region of said transistor through said second contact hole, by forming a first conductive layer in said second contact hole;
• forming a second insulating layer on the bit line, on the pad conductive layer and on the interlayer insulating film;
• forming a third contact hole which partially exposes said pad conductive layer on said source region of said transistor, by patterning said second insulating layer;
• and
• forming a storage electrode which is electrically connected to said pad conductive layer and to said source region of said transistor through said third contact hole by blanket forming a second conductive layer on the second insulating layer, and patterning said second conductive layer.