Process to personalize master slice wafers and fabricate high density VLSI components with a single masking step
AssigneeLockheed Martin Corporation
InventorJai P. Bansal
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Abstract
A method of making gate array ASIC components from a master slice wafer having a first conducting layer containing logic elements, a second conducting layer containing first electrically conducting elements extending in a first direction, and a third conducting layer comprises interconnecting at least some of the logic elements to one another with a single masking process step by defining, on the third conducting layer, second conducting elements connected to the first electrically conducting elements to define connections between the logic elements.
Claims16
A method of making gate array ASIC components from a wafer having a first conducting layer interconnecting logic elements formed on the wafer and second and third conducting layers, wherein each said logic element is capable of performing a logic function, said first, second and third conducting layers being insulated from one another by insulating layers, and said second conducting layer containing first electrically conducting elements extending in a first direction, said second conducting layer being the same for all ASIC designs, comprising
- interconnecting at least some of the logic elements to one another with a single masking process step to complete an ASIC design by defining on said third conducting layer at least one second conducting element connected to at least one of said first electrically conducting elements formed in said second conducting layer to define connections between the logic elements.
A method of making gate array ASIC components from a wafer having a first conducting layer interconnecting logic elements formed on the wafer and second and third conducting layers, said first, second and third conducting layers being insulated from one another by insulating layers, and said second conducting layer containing first electrically conducting elements extending in a first direction, said second conducting layer being the same for all ASIC designs, wherein said first electrically conducting elements are unconnected to said logic elements, comprising
- interconnecting at least some of the logic elements to one another with a single masking process step to complete an ASIC design by defining on said third conducting layer at least one second conducting element connected to at least one of said first electrically conducting elements formed in said second conducting layer to define connections between the logic elements.
Dependencies are inferred from the claim text.