US 5,856,693 A · Semiconductor integrated circuit device containing MOS protection circuit

Abstract

A semiconductor integrated circuit device containing a protection MOSFET. This MOSFET has source and drain regions and a channel region formed in a semiconductor substrate. The channel region is disposed between the source and drain regions. The source region is made of a first lightly doped region and a first heavily doped region. The first lightly doped region is adjacent to a first end of the channel region. The drain region is made of a second lightly doped region and a second heavily doped region. The second lightly doped region is adjacent to a second end of the channel region. The second end of the channel region is positioned on an opposite side to that of the first end. A distance from the second end of the channel region to an opposing end of the second heavily doped region is longer than a distance from the first end of the channel region to an opposing end of the first heavily doped region. Even if the snapback voltage of the MOSFET fluctuates from place to place in the same MOSFET, the snapback phenomenon tends to occur within the entire drain region almost simultaneously, enabling to improve the ESD breakdown resistance of the protection MOSFET.

Claims16

Dependent claims

In a semiconductor integrated circuit device containing a protection MOSFET with an LDD structure, said protection MOSFET comprising:

a source region formed in a semiconductor substrate, said source region being made of a first lightly doped region and a first heavily doped region;
a drain region formed in said substrate, said drain region being made of a second lightly doped region and a second heavily doped region;
a channel region formed in said substrate between said source region and said drain region;
and
a first refractory-metal silicide layer formed on said first heavily doped region and a second refractory-metal silicide layer formed on said second heavily doped region;
said first lightly doped region being adjacent to a first end of said channel region,
said second lightly doped region being adjacent to a second end of said channel region, said second end of said channel region being positioned on an opposite side to that of said first end,
said first refractory-metal silicide layer covering an entirety of said first heavily doped region and said second refractory-metal silicide layer covering said second heavily doped region and an exposed part of said second lightly doped region, and
a distance from said second end of said channel region to an opposing end of said second heavily doped region being longer than a distance from said first end of said channel region to an opposing end of said first heavily doped region.

6 more elements

In a semiconductor integrated circuit device containing a protection MOSFET with an LDD structure, said protection MOSFET comprising:

a source region formed in a semiconductor substrate, said source region being made of a first lightly doped region and a first heavily doped region;
a drain region formed in said substrate, said drain region being made of a second lightly doped region and a second heavily doped region;
and
a channel region formed in said substrate between said source region and said drain region;
said first lightly doped region being adjacent to a first end of said channel region,
said second lightly doped region being adjacent to a second end of said channel region, said second end of said channel region being positioned on an opposite side to that of said first end,
said second heavily doped region being composed of island-like parts, said parts being placed at positions corresponding to contact holes provided for said drain region, respectively, and
a distance from said second end of said channel region to an opposing end of said second heavily doped region being longer than a distance from said first end of said channel region to an opposing end of said first heavily doped region.

5 more elements

A semiconductor integrated circuit device containing a protection MOSFET with an LDD structure, said MOSFET comprising:

a semiconductor substrate of a first conductivity type;
a gate oxide layer formed on said substrtate;
a gate electrode formed on said gate oxide layer;
a first sidewall spacer formed on said substrate adjacent to said gate electrode, said first sidewall spacer being disposed on one side of said gate electrode;
a second sidewall spacer formed on said substrate adjacent to said gate electrode, said second sidewall spacer being disposed on the other side of said gate electrode;
a first lightly doped region of a second conductivity type formed in said substrate, said second conductivity type being opposite in polarity to said first conductivity type;
said first lightly doped region being disposed on a side of said first sidewall spacer and extending to an opposing end of said gate electrode;
a first heavily doped region of said second conductivity type formed in said substrate;
said first heavily doped region being disposed on said first lightly doped region and extending to an opposing end of said first sidewall spacer;
said first lightly doped region and said first heavily doped region constituting a source region of said MOSFET;
a second lightly doped region of said second conductivity type formed in said substrate;
said second lightly doped region being disposed on a side of said second sidewall spacer and extending to an opposing end of said gate electrode;
a second heavily doped region of said second conductivity type formed in said substrate;
said second heavily doped region being disposed on said second lightly doped region and not extending to an opposing end of said second sidewall spacer;
said second lightly doped region and said second heavily doped region constituting a drain region of said MOSFET;
a channel region formed in said substrate, said channel region being disposed under said gate oxide layer between said first lightly doped region and said second lightly doped region;
an interlayer insulator film formed over said substrate to cover said MOSFET, said interlayer insulator film having a first contact hole that exposes said first heavily doped region and a second contact hole that exposes said second heavily doped region;
and
a patterned interconnection film formed on said interlayer insulator film, said interconnection film being contacted with said first heavily doped region through said first contact hole and being contacted with said second heavily doped region through said second contact hole;
wherein a distance between opposing ends of said channel region and said second heavily doped region is longer than a distance between opposing ends of said channel region and said first heavily doped region.

17 more elements

Dependencies are inferred from the claim text.

Semiconductor integrated circuit device containing MOS protection circuit

Life of this patent

Semiconductor integrated circuit device containing MOS protection circuit

Life of this patent

Abstract

Claims16