Voltage-clamped power accumulation-mode MOSFET

An accumulation-mode field-effect transistor comprising:

• a semiconductor material;
• a gate positioned in a trench at a surface of said semiconductor material and separated from said semiconductor material by a gate insulating layer, said gate defining a transistor cell, said cell containing substantially only material of a first conductivity type;
• a heavily-doped region of said first conductivity type located at a surface of said cell;
• a lightly-doped region of said first conductivity type adjacent said heavily-doped region;
• a PN junction within said semiconductor material, said PN junction forming a diode, said diode being connected in parallel with a current path through said cell, wherein said PN junction extends to a level in said semiconductor material below a bottom of said trench.

An accumulation-mode field-effect transistor comprising:

• a semiconductor material;
• a gate positioned in a trench at a surface of said semiconductor material and separated from said semiconductor material by a gate insulating layer, said gate defining a transistor cell, said cell containing substantially only material of a first conductivity type;
• a heavily-doped region of said first conductivity type located at a surface of said cell;
• a lightly-doped region of said first conductivity type adjacent said heavily-doped region;
• a PN junction extending from sad trench within said semiconductor material, said PN junction forming a diode, said diode being connected in parallel with a current path through said cell, wherein said PN junction has a deepest point which is at a location lower than a point at which said PN junction meets said trench.

An accumulation-mode field-effect transistor comprising:

• a semiconductor material, said semiconductor material including an epitaxial layer formed on a substrate;
• a gate positioned in a trench at a surface of said semiconductor material and separated from said semiconductor material by a gate insulating layer, said gate defining a transistor cell, said cell containing substantially only material of a first conductivity type, said trench extending through said epitaxial layer and into said substrate;
• a heavily-doped region of said first conductivity type located at a surface of said cell;
• a lightly-doped region of said first conductivity type adjacent said heavily-doped region;
• a region of a second conductivity type located on an opposite side of said gate from said cell, a PN junction being formed at a junction of said region of second conductivity type and said substrate, said PN junction forming a diode, said diode being connected in parallel with a current path through said cell, wherein said diode is adapted so as to have a breakdown voltage which is less than a voltage required to damage said gate insulating layer when said transistor is in an off condition.