Heterojunction field effect transistor
AssigneeNEC Corporation
InventorTatsuo Nakayama
Life of this patent
Estimating the term…
Abstract
A heterojunction field effect transistor having an InP substrate, comprising a buffer layer formed between an active layer where a carrier travels and said InP substrate, wherein said buffer layer has at least two cycles of superlattices, each of said superlattices being formed of at least one semiconductor selected from the group consisting of Al.sub.x In.sub.1-x P (0.1.ltoreq.x.ltoreq.1), Ga.sub.x In.sub.1-x P (0.ltoreq.x.ltoreq.1), Al.sub.x Ga.sub.1-x As (0.ltoreq.x.ltoreq.1), and Al.sub.x In.sub.1-x As (0.5.ltoreq.x.ltoreq.1), and at least one semiconductor selected from the group consisting of InP and In.sub.0.52 Al.sub.0.48 As.
Claims23
A heterojunction field effect transistor having an InP substrate, comprising a buffer layer formed between an active layer where a carrier travels and said InP substrate, wherein said buffer layer comprises at least two cycles of superlattices, each of said superlattices being formed of at least one semiconductor selected from the group consisting of Al.sub.x In.sub.1-x P (0.1.ltoreq.x.ltoreq.1), Ga.sub.x In.sub.1-x P (0.ltoreq.x.ltoreq.1), Al.sub.x Ga.sub.1-x As (0.ltoreq.x.ltoreq.1) and Al.sub.x In.sub.1-x As (0.5.ltoreq.x.ltoreq.1), and at least one semiconductor selected from the group consisting of InP and In.sub.0.52 Al.sub.0.48 As.
A heterojunction field effect transistor having an InP substrate, comprising a buffer layer formed between an active layer where a carrier travels and said InP substrate, wherein said buffer layer comprises an In.sub.0.52 Al.sub.0.48 As layer and at least one layer selected from the group consisting of an Al.sub.x In.sub.1-x P (0.1.ltoreq.x.ltoreq.1) layer, a Ga.sub.x In.sub.1-x P (0.ltoreq.x.ltoreq.1) layer, an Al.sub.x Ga.sub.1-x As (0.ltoreq.x.ltoreq.1) layer and an Al.sub.x In.sub.1-x As (0.5.ltoreq.x.ltoreq.1) layer.
A heterojunction field effect transistor having an InP substrate, comprising a buffer layer formed between an active layer where a carrier travels and said InP substrate, wherein said buffer layer comprises an InP layer and at least one layer selected from the group consisting of an Al.sub.x Ga.sub.1-x As (0.ltoreq.x.ltoreq.1) layer, and an Al.sub.x In.sub.1-x As (0.5.ltoreq.x.ltoreq.1) layer;
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- wherein an AlAs composition ratio of said AlGaAs layer is preferably 0.3 molecular fraction.
A heterojunction field effect transistor having an InP substrate, comprising a buffer layer formed between an active layer where a carrier travels and said InP substrate, wherein said buffer layer comprises an InP layer and at least one layer selected from the group consisting of an Al.sub.x In.sub.1-x P (0.1.ltoreq.x.ltoreq.1) layer, a Ga.sub.x In.sub.1-x P (0.ltoreq.x.ltoreq.1) layer, an Al.sub.x Ga.sub.1-x As (0.ltoreq.x.ltoreq.1) layer, and an Al.sub.x In.sub.1-x As (0.5.ltoreq.x.ltoreq.1) layer;
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- wherein a material consisting of said active layer is at least one selected from the group consisting of GaInAs, InP, GaInAsP, InSb, InGaSb.
A heterojunction field effect transistor obtained by sequentially forming a superlattice consisting of at least two cycles of In.sub.0.52 Al.sub.0.48 As layers and InP layers, a GaInAs active layer, an AlInAs spacer layer, an AlInAs carrier supply layer and an AlInAs Schottky layer on an InP substrate, and arranging a source electrode, a drain electrode and a gate electrode on a resultant structure.
Dependencies are inferred from the claim text.