US 5,856,227 AGranted

Method of fabricating a narrow polycide gate structure on an ultra-thin gate insulator layer

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsChen-Hua Yu, Chia-Shiung Tsai

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Abstract

A process for creating a MOSFET device, with a narrow polycide gate structure, on an ultra-thin gate oxide, has been developed. The process features partially etching of a polysilicon layer, used in the polycide structure, to a level in which only a thin residual layer of the polysilicon remains. After formation of a lightly doped source and drain region, formed via ion implantation through the thin residual polysilicon layer, an oxidation is performed to convert the thin residual polysilicon layer, to an oxide layer. The ability to complete the patterning of the polysilicon layer using oxidation procedures, avoids the risk of RIE trenching or pitting, that can occur if the polysilicon layer is patterned using only RIE procedures.

Claims20

Dependent claims

A method for fabricating a MOSFET device, on a semiconductor substrate, comprising the steps of:

forming field oxide regions in said semiconductor substrate;
growing a gate insulator layer on said semiconductor substrate, in areas not covered by said field oxide regions;
depositing a polysilicon layer;
depositing a metal silicide layer on said polysilicon layer;
depositing a first insulator layer on said metal silicide layer;
forming a photoresist layer into a mask on a top surface of said first insulator layer;
using said mask for patterning of said first insulator layer, for patterning of said metal silicide layer, and for patterning of a top portion of said polysilicon layer, to create a polycide gate structure having exposed sides, comprised of said metal silicide overlying said top portion of said polysilicon layer, on said gate insulator layer, while leaving a residual bottom portion of said polysilicon layer, in regions not covered by said photoresist mask;
removal of said photoresist mask;
ion implanting a first conductivity imparting dopant, through said residual bottom portion of said polysilicon layer, into a region of said semiconductor substrate, not covered by said polycide gate structure, to create a lightly doped source and drain region;
oxidizing to grow a silicon oxide sidewall layer on the exposed sides of said polycide gate structure, while converting said residual bottom portion of said polysilicon layer, to a first silicon oxide layer;
depositing a second insulator layer;
anisotropic etching of said second insulator layer to create an insulator spacer, overlying said silicon oxide sidewall layer;
ion implanting a second conductivity imparting dopant, into a region of said semiconductor substrate, not covered by said polycide gate structure, not covered by said insulator spacer, and not covered by said silicon oxide sidewall layer, to create a heavily doped source and drain region;
depositing an interlevel insulator layer;
opening a contact hole in said interlevel insulator layer, to expose the top surface of said heavily doped source and drain region, and opening a contact hole in said interlevel insulator layer and in said first insulator layer, to expose the top surface of said polycide gate structure;
and
forming metal contact structures to said heavily doped source and drain region, and to said polycide gate structure.

14 more elements

A method of fabricating a polycide gate structure, on a gate oxide layer, for a MOSFET device, on a semiconductor substrate, in which the formation of said polycide gate structure is performed via a dry etching procedure, featuring the removal of only a top portion of the polysilicon layer, used in the polycide gate structure, comprising the steps of:

growing said gate oxide layer on said semiconductor substrate;
depositing said polysilicon layer;
depositing a tungsten silicide layer;
depositing a first silicon oxide layer;
forming a photoresist layer into a mask on the top surface of said first silicon oxide layer;
using said mask to create said polycide gate structure having exposed sides, on said gate oxide layer, via anisotropic dry etching of said first silicon oxide layer, via anisotropic dry etching of said tungsten silicide layer, and via anisotropic dry etching of said top portion of said polysilicon layer, leaving a residual bottom portion of said polysilicon layer, in regions not covered by said photoresist mask;
removal of said photoresist mask;
ion implanting a first conductivity imparting dopant though said residual bottom portion of said polysilicon layer, into a region of said semiconductor substrate, not covered by said polycide gate structure, to create a lightly doped source and drain region;
oxidizing to convert said residual bottom portion of said polysilicon layer to a second silicon oxide layer, while forming a silicon oxide sidewall layer on the exposed sides of said polycide gate structure;
depositing an insulator layer;
anisotropic dry etching of said insulator layer to form an insulator spacer on the sides of said polycide gate structure;
ion implanting a second conductivity imparting dopant into a region of said semiconductor substrate, not covered by said polycide gate structure, and not covered by said insulator spacers, to create a heavily doped source and drain region;
depositing an interlevel insulator layer;
opening a contact hole in said interlevel insulator layer, to expose the top surface of said heavily doped source and drain region, and opening a contact hole in said interlevel insulator layer and in said first silicon oxide layer, to expose the top surface of said polycide gate structure;
and
forming metal contact structures to said heavily doped source and drain region, and to said polycide gate structure.

13 more elements

Dependencies are inferred from the claim text.