Method for manufacturing self-aligned split-gate flash memory cells

A method for manufacturing self-aligned split-gate flash memory cells comprising:

• providing a substrate and forming a tunneling oxide layer on said substrate;
• depositing a first poly-silicon layer on said tunneling oxide layer;
• depositing a first thermal oxide layer on the first poly-silicon layer and then depositing a first nitride layer on said first thermal oxide layer;
• depositing a second thermal oxide layer over said first nitride layer;
• depositing a second poly-silicon layer over the second thermal oxide layer and depositing a second dielectric structure over said second poly-silicon layer;
• forming a plurality of gates using a self-aligned etching process;
• depositing a third thermal oxide layer over the plurality of gates and the substrate, and depositing a second nitride layer over said third thermal oxide layer;
• forming a plurality of nitride spacers by executing a back etch to said second nitride layer, and then depositing an oxide layer over the nitride spacers, the plurality of gates and the substrate;
• forming a plurality of oxide spacers around and between the plurality of gates by executing a back etch to said oxide layer;
• forming a plurality of sources by ion implantation by using said oxide spacers as a mask, and then removing said oxide spacers;
• forming a photoresist over said substrate except for regions between the plurality of gates by photolithography and then executing implantation to form a plurality of drains;
• removing said photoresist;
• depositing a fourth thermal oxide layer over the plurality of gates and the substrate, depositing a third poly-silicon layer over said fourth thermal oxide layer, and depositing a metal silicide layer over said third poly-silicon layer;
• and
• etching said third poly-silicon layer.