Method of fabricating a high density EEPROM cell

A method of fabricating and EEPROM cell structure in a semiconductor substrate, the method comprising:

• forming a layer of silicon oxide having a first thickness on the silicon substrate;
• introducing N-type dopant into the semiconductor substrate to define a buried region beneath the silicon oxide layer;
• forming a tunnel window opening in the silicon oxide layer to expose a surface area of the buried region;
• forming a layer of tunnel oxide in the tunnel window opening on the exposed surface area of the buried region, the tunnel oxide having a second thickness that is less than the first thickness;
• forming a first layer of polysilicon over the structure resulting from the foregoing steps;
• forming a layer of dielectric material on the first polysilicon layer;
• forming a second layer of polysilicon on the layer of dielectric material, the second layer of polysilicon, the layer of dielectric material and the first polysilicon layer defining a poly-2/dielectric.backslash.poly-1 sandwich;
• anisotropically etching the poly-2.backslash.dielectric.backslash.poly-1 sandwich to define first and second spaced-apart poly-2.backslash.dielectric.backslash.poly-1 stacks;
• utilizing the first and second poly2.backslash.dielectric.backslash.poly-1 stacks in a self-aligned ion implantation step to define a drain.backslash.bit line region of N-type conductivity formed in the semiconductor substrate and in spaced-apart relationship to the buried region to define an access transistor substrate channel region therebetween, and to define a source region of N-type conductivity formed in the semiconductor substrate and in spaced-apart relationship to the buried region to define the storage cell substrate channel region therebetween;
• wherein the first poly-2.backslash.dielectric.backslash.poly-1 stack includes a poly-1 access transistor floating gate having a first portion formed over the axis transistor substrate channel region and separated therefrom by silicon oxide having the first thickness and having a second portion formed over a first portion of the buried region and separated therefrom by tunnel oxide and a poly-2 access transistor control gate formed over the access transistor floating gate and separated therefrom by dielectric material;
• and
• wherein the second poly-2/dielectric.backslash.poly-1 stack includes a poly-1 storage cell floating gate having a first portion formed over the storage cell channel region and separated therefrom by silicon oxide having the first thickness and having a second portion formed over a second portion of the buried region and separated therefrom by tunnel oxide and a poly-2 storage cell control gate formed over the storage cell floating gate and separated therefrom by dielectric material.