US 5,856,221 AGranted

Process for forming an integrated circuit comprising non-volatile memory cells and side transistors of at least two different types, and corresponding IC

OwnerCesare Clementi, Gabriella Ghidini +1inventors

InventorsCesare Clementi, Gabriella Ghidini, Carlo Riva

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Abstract

A process or forming an integrated circuit calls for the provision of at least one matrix of non-volatile memory cells including an intermediate dielectric multilayer comprising a lower silicon oxide layer, an intermediate silicon nitride layer and an upper silicon oxide layer. The process calls for the simultaneous provision in zones peripheral to the memory cells of at least one first and one second transistor type each having a gate dielectric of a first and a second thickness respectively. After formation of the floating gate of the cells with a gate oxide layer and a polycrystalline silicon layer and the formation of the lower silicon oxide layer and of the intermediate silicon nitride layer, the process in accordance with the present invention includes removal of said layers from the zones peripheral to the matrix, and formation of a first silicon oxide layer over the substrate in the areas of both types of transistor. The process further includes removal of the preceding layer from areas assigned only to the transistors of the second type; deposition of said upper silicon oxide layer over the memory cells, over the first silicon oxide layer in the areas of the transistors of the first type and over the substrate in the areas of the transistors of the second type; and formation of a second silicon oxide layer in the areas of both types of peripheral transistors.

A process for forming an integrated circuit in a monocrystalline silicon substrate having implemented thereon a matrix of non-volatile memory cells each having a floating gate and a control gate, each floating gate and control gate being electroconductive and insulated electrically from each other by means of an intermediate dielectric multilayer having a lower silicon oxide layer, an intermediate silicon nitride layer, and an upper silicon oxide layer and the substrate also having simultaneous implementation, in peripheral zones of the memory cells, at least first and second transistors having a gate dielectric of a first and second thickness respectively, the process comprising the steps of:

(A) forming a gate oxide layer, a polycrystalline silicon layer, the lower silicon oxide layer, and the intermediate silicon nitride layer;
(B) removal of the lower silicon oxide layer, the intermediate silicon nitride layer, the polycrystalline silicon layer, and the gate oxide layer from the peripheral zones;
(C) formation of a first silicon oxide layer over the substrate in the areas of the first and the second transistors;
(D) removal of the first silicon oxide layer from the areas of the substrate including only the second transistor;
(E) after step (D), simultaneous deposition of a silicon oxide layer over the memory cells and the peripheral zones in which the at least first and second transistors are formed, the silicon oxide layer forming the upper silicon oxide layer of the intermediate dielectric multilayer of the memory cells, and at least part of the gate dielectrics of the first and second transistors, the silicon oxide layer being deposited over the first silicon oxide layer in the areas including the first transistor, and over the substrate in the areas including the second transistor;
and
(F) formation of a second silicon oxide layer in the areas of the substrate including the transistors of both the first and the second transistors.

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Abstract

Claims17