US 5,856,219 AGranted

Method of fabricating a high-density dynamic random-access memory

AssigneeMatsushita Electric Industrial Co., Ltd.

InventorsYasushi Naito, Yutaka Ito, Yuichi Hirofuji

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Abstract

The invention relates to a high-density DRAM fabrication technique for forming a source/drain contact between word lines in a self-alignment manner, with the offset length between a source region and a drain region of a peripheral transistor maintained at an adequate value. After gate electrodes (i.e. word lines) are formed, a first insulating layer, which is thin enough not to block up space defined between the word lines, is deposited. The source/drain contact is etched as deep as the first insulating layer is thick to form an extraction electrode made of polycrystalline silicon. A second insulating layer is deposited until a spacer thickness (i.e. the sum of the film thickness of the second insulating layer and the film thickness of the first insulating layer) for determining the offset length is obtained. The first and second insulating layers are etched back for a distance corresponding to the sum of the film thickness of the second insulating layer and the film thickness of the first insulating layer so that a spacer (i.e. the residue of the insulating layers) is left on the side walls of the gate electrode. An implantation of highlevel impurities is performed to form heavily doped source and drain regions of a peripheral transistor. In-cell self-align contact is made possible while maintaining the offset length of the heavily doped source and drain regions

Claims5

Dependent claims

A method of fabricating a high-density dynamic random-access memory (DRAM) comprising memory cells and a peripheral circuit, said DRAM fabrication method comprising the sequential steps of:

(a) forming gate electrodes and upper insulating layers on top of said gate electrodes respectively in a first region of a substrate in which said memory cells are formed as well as in a second region of the substrate in which said peripheral circuit is formed;
(b) forming source/drain regions in said first region:
(c) depositing a first insulating layer on the substrate on which said gate electrodes are formed;
(d) carrying out an anisotropic etching selectively to said first insulating layer in said first region to such an extend that a first side wall spacer composed of said first insulating layer is formed on the sides of said gate electrodes whereby source/drain contact areas in said first region are exposed, and thereafter forming extraction electrodes on said source/drain contact areas in said first region;
(e) depositing a second insulating layer on the substrate;
(f) carrying out an anisotropic etching t said first and second insulating layers in said second region, for selective removal in such a manner that a second side wall spacer composed of said first and second insulating layers is formed on the sides of said gate electrodes whereby at least source/drain contact areas in said second region are exposed;
and (g) forming heavily doped source and drain regions in said second region by introducing impurities of a high concentration using partly or entirely said second side wall spacer as a mask.

4 more elements

Dependencies are inferred from the claim text.