Method of fabricating a CMOS transistor

A method of fabricating a CMOS transistor, comprising:

• forming an N-well in a portion of a P-substrate;
• defining field regions and active regions on said N-well and said P-substrate using an element separation process;
• forming a field oxide film in said field regions, respectively;
• forming a first N.sup.+ diffusion region between said active regions at an edge of said N-well;
• forming a common gate electrode on said P-substrate and said N-well;
• forming a first source and drain in said N-well having said common sate electrode as a first gate to form a PMOS transistor;
• forming a second source and drain in said P-substrate having said common gate electrode as a second gate to form an NMOS transistor;
• forming a second N.sup.+ diffusion region along said edge of said N-well, wherein said second N.sup.+ diffusion region is connected to said first N.sup.+ diffusion region at said edge of said N-well;
• forming an interlayer insulation film on the resulting structure after forming said second N.sup.+ diffusion region;
• and
• connecting, through a metal contact process, said first junction portion and said third junction portion with a first metal wiring, and second junction portion and said fourth junction portion with a second metal wiring.